US3201574A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flexible logic circuit
Assignee: RCA Corp
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Filing: 1960-10-07
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Granted: 1965-08-17
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Expires: 1980-10-07
Abstract
No abstract record available.
Inventors
- 👤 Michael E Szekaly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:36
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/501; G06F7/57; G06F7/575; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09403; H03K19/09407; H03K19/173; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 1
Claim 1
Independent Claim
92 words
A PARALLEL BINARY SUBTRACTOR COMPRISING, IN COMBINATION, N BINARY SUBTRACTION STAGES, EACH FOR RECEIVING A BORROW, MINUEND AND SUBTRAHEND BINARY QUANTITY OF DIFFERENT RANK, AND EACH FOR PRODUCING A BORROW OUTPUT; N MEMORIES, EACH FOR RECEIVING AND STORING A BORROW OUTPUT OF DIFFERENT RANK, AND EACH FOR APPLYING ITS STORED BORROW QUANTITY TO THE SUBTRACTION STAGE OF NEXT HIGHER RANK; AND MEANS FOR CONVERTING EACH SAID BINARY SUBTRACTION STAGE TO A BINARY ADDER STAGE AFTER ALL BORROW OUTPUTS ARE STORED, WHEREBY EACH SAID STAGE PRODUCES A DIFFERENCE OUTPUT QUANTITY OF DIFFERENT RANK.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-08-16 | 1969-02-15 | 1969-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-08-16 | 1973-02-15 | 1973-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-08-16 | 1977-02-15 | 1977-08-17 | $7700.00 | Window Closed / Lapsed |