Parallel digital adder system

Claim 1

A PARALLEL BINARY DIGITAL ADDER SYSTEM FOR SUMMING A PAIR OF NUMERICAL VALUES EACH REPRESENTED BY PLURAL BINARY INPUT SIGNALS RANGING IN SEQUENCE TO REPRESENT BINARY DIGITS FROM MOST SIGNIFICANT TO LEAST-SIGNIFICANT ORDERS, COMPRISING: A PLURALITY OF ADDER CIRCUITS EACH HAVING FIRST INPUT TERMINALS FOR RESPECTIVELY RECEIVING A PAIR OF SAID INPUT BINARY SIGNALS REPRESENTING DIGITS OF ONE ORDER, AND SECOND INPUT TERMINALS FOR RECEIVING CARRY SIGNALS, EACH OF SAID ADDER CIRCUITS INCLUDING MEANS TO GENERATE A SUM SIGNAL REPRESENTATIVE OF THE SUM OF THE RECEIVED BINARY INPUT SIGNALS, AND MEANS TO GENERATE A CARRY SIGNAL REPRESENTATIVE OF A CARRY DIGIT FROM THE ADDER CIRCUIT; MEANS CONNECTING SAID ADDER CIRCUITS IN A SERIAL SEQUENCE WHEREBY CARRY SIGNALS FROM EACH ADDER CIRCUIT ARE APPLIED TO SAID SECOND INPUT TERMINALS OF THE NEXT ORDER ADDER CIRCUIT; A FIRST SENSING MEANS TO FORM ONE AUXILIARY CARRY SIGNAL UPON THE OCCURRENCE OF SIGNALS APPLIED AT THE INPUT TERMINALS OF A FIRST SELECT GROUP OF SAID ADDER CIRCUITS WHICH RESULT IN THE PROPAGATION OF A CARRY SIGNAL THROUGH ALL OF SAID FIRST SELECT GROUP OF ADDER CIRCUITS; MEANS FOR APPLYING SAID ONE AUXILIARY CARRY SIGNAL TO THE SECOND INPUT TERMINALS OF THE MOST-SIGNIFICANT ORDER ADDER CIRCUIT IN SAID FIRST SELECT GROUP OF ADDER CIRCUITS, A SECOND SENSING MEANS TO FORM ANOTHER AUXILIARY CARRY SIGNAL UPON THE OCCURENCE OF SIGNALS APPLIED AT THE INPUT TERMINALS OF A SECOND SELECT GROUP OF SAID ADDER CIRCUITS WHICH INCLUDES SAID FIRST SELECT GROUP OF ADDER CIRCUITS, SAID SECOND SENSING MEANS FOR PROPAGATING A CARRY SIGNAL THROUGH ALL OF SAID SECOND GROUP OF ADDER CIRCUITS; AND MEANS FOR APPLYING SAID OTHER AUXILIARY CARRY SIGNAL TO THE SECOND INPUT TERMINALS OF THE MOST-SIGNIFICANT ORDER ADDER CIRCUIT IN SAID SECOND SELECT GROUP OF ADDER CIRCUITS.