Peak detecting and reshaping circuit

Claim 1

A PEAK DETECTOR AND PULSE SHAPER COMPRISING A FIRST TRANSISTOR CONNECTED IN THE GROUNDED COLLECTOR CONFIGURATION, MEANS INCLUDING FIRST AND SECOND SERIES RESISTORS CONNECTED IN CIRCUIT WITH THE EMITTER OF THE FIRST TRANSISTOR, MEANS CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR FOR MAINTAINING THE FIRST TRANSISTOR NON-CONDUCTIVE IN THE ABSENCE OF PEAKS OF AN INPUT SIGNAL, MEANS FOR APPLYING AN INPUT SIGNAL INCLUDING PEAKS TO THE BASE OF SAID FIRST TRANSISTOR, A SECOND TRANSISTOR CONNECTED IN THE GROUNDED BASE CONFIGURATION, SAID SECOND TRANSISTOR HAVING ITS EMITTER CONNECTED BETWEEN SAID FIRST AND SECOND RESISTORS WHEREBY THE EMITTER CURRENT PATHS OF SAID FIRST AND SECOND TRANSISTORS INCLUDE SAID SECOND RESISTOR IN COMMON MEANS FOR RENDERING SAID SECOND TRANSISTOR CONDUCTING WITH THE COLLECTOR CURRENT THEREOF BEING THEREBY REPRESENTATIVE OF CLIPPED PEAKS OF SAID INPUT SIGNAL, DIFFERENTIATING MEANS INCLUDING AN INDUCTOR AND A RESISTOR CONNECTED IN PARALLEL AND COUPLED IN THE COLLECTOR OF SAID SECOND TRANSISTOR FOR DEVELOPING A DIFFERENTIATED OUTPUT VOLTAGE ACROSS SAID INDUCTOR REPRESENTATIVE OF THE RATE OF CHANGE OF THE COLLECTOR CURRENT, SAID OUTPUT VOLTAGE HAVING ZERO CROSSING POINTS CORRESPONDING TO PEAKS OF SAID COLLECTOR CURRENT, AND MEANS COUPLED TO SAID DIFFERENTIATING MEANS IN RECEIVING RELATION TO SAID DIFFERENTIATED OUTPUT VOLTAGE FOR GENERATING PULSES IN RESPONSE TO AND HAVING LEADING EDGES IN COINCIDENCE WITH SAID ZERO CROSSING POINTS.