Frequency generating system

Claim 1

AN ELECTRICAL SYSTEM FOR PRODUCING OUTPUT SIGNALS HAVING ANY OF A PLURALITY OF DESIRED FREQUENCIES INCLUDING A MASTER OSCILLATOR CAPABLE OF EMITTING FREQUENCIES OVER A DESIRED FREQUENCY RANGE AND MEANS FOR VARYING THE OUTPUT FREQUENCY OF SAID MASTER OSCILLATOR, A TIMER STANDARD OSCILLATOR CAPABLE OF PRODUCING AN OUTPUT SIGNAL WHICH IS CLOSELY CONTROLLED TO A CONSTANT FREQUENCY, FREQUENCY DIVIDING MEANS CONNECTED TO RECEIVE THE OUTPUT OF SAID MASTER OSCILLATOR FOR DIVIDING SAID OUTPUT BY ANY OF A NUMBER OF DESIRED INTEGERS INCLUDING A FIRST BINARY DIVIDER AND A SERIES OF N DECADE COUNTERS WITH SWITCHES FOR DIVIDING SAID OUTPUT BY AN INTEGER UP TO 10N, COMPARING MEANS FOR COMPARING THE OUTPUTS FROM SAID TIME STANDARD OSCILLATOR AND SAID DIVIDING MEANS AND PRODUCING AN OUTPUT SIGNAL HAVING A POLARITY AND AVERAGE VOLTAGE PROPORTIONAL TO THE DIRECTION AND EXTENT OF DEPARTURE OF THE DIVIDING MEANS PULSE FROM THE TIME STANDARD PULSE INCLUDING A FIRST FLIP-FLOP CIRCUIT AND A SECOND FLIP-FLOP CIRCUIT, A FIRST PULSE PRODUCING CIRCUIT FOR PRODUCING A PULSE OF A CONSTANT PULSE DURATION, A FIRST GATE CIRCUIT CONNECTED TO SAID FIRST FLIP-FLOP CIRCUIT AND TO SAID FIRST PULSE PRODUCING CIRCUIT TO WHICH THE PULSE FROM SAID FIRST PRODUCING CIRCUIT IS SUPPLIED, A SECOND GATE CIRCUIT CONNECTED TO SAID SECOND FLIP-FLOP CIRCUIT AND TO SAID PULSE PRODUCING CIRCUIT TO WHICH THE PULSE FROM SAID FIRST PULSE PRODUCING CIRCUIT IS SUPPLIED AT THE OPPOSITE POLARITY FROM SAID FIRST GATE, A THIRD GATE CONNECTED TO SAID FIRST FLIP-FLOP CIRCUIT, A SECOND PULSE PRODUCING CIRCUIT CONNECTED TO RECEIVE AN INPUT FROM SAID THIRD GATE CIRCUIT PRODUCING A RESET PULSE HAVING A GREATER DURATION THAN THAT OF SAID FIRST NAMED PULSE AND CONNECTED TO SAID DIVIDING MEANS AND TO SAID FIRST AND SECOND FLIP-FLOP CIRCUITS TO RESET SAID DIVIDING MEANS AND SAID CIRCUITS AT THE END OF SAID RESET PULSE, SUCH THAT WHEN THE OUTPUT PULSE FROM SAID DIVIDING MEANS LEADS THAT FROM SAID TIME STANDARD OSCILLATOR, SAID FLIP-FLOP CIRCUIT IS ENERGIZED THEREBY DISABLING SAID FIRST GATE AND ENABLING SAID THIRD GATE AND SAID OUTPUT PULSE IS ALSO SUPPLIED TO SAID FIRST PULSE PRODUCING CIRCUIT CAUSING SAID CIRCUIT TO EMIT A PULSE TO SAID SECOND GATE OF A PROPER POLARITY TO CAUSE SAID AUTOMATIC FREQUENCY CONTROL CIRCUIT TO REDUCE THE OUTPUT FREQUENCY OF SAID MASTER OSCILLATOR; AND WHEN THE OUTPUT PULSE FROM SAID DIVIDING MEANS LAGS THAT FROM SAID TIME STANDARD OSCILLATOR, THE PULSE FROM SAID OSCILLATOR ENERGIZES SAID SECOND FLIP-FLOP CIRCUIT WHICH CLOSES SAID SECOND GATE AND CAUSES SAID FIRST PULSE PRODUCING CIRCUIT TO EMIT A PULSE TO SAID FIRST GATE OF A PROPER POLARITY TO CAUSE SAID AUTOMATIC FREQUENCY CONTROL CIRCUIT TO INCREASE THE OUTPUT FREQUENCY OF SAID MASTER OSCILLATOR; AND IN AUTOMATIC FREQUENCY CONTROL CIRCUIT RECEIVING THE OUTPUT OF SAID COMPARING MEANS AND CONNECTING IT TO SAID MEANS FOR VARYING THE OUTPUT FREQUENCY OF SAID MASTER OSCILLATOR AND FOR FINALLY LOCKING THE PHASE OF THE DIVIDED MASTER OSCILLATOR OUTPUT TO THAT OF THE TIME STANDARD OSCILLATOR.