Serial to parallel converter for data signals

Claim 1

IN A RECEIVER FOR START-STOP BINARY CODE CHARACTER ELEMENTS, A MULTISTAGE SHIFT REGISTER, RECEIVING MEANS FOR SERIALLY APPLYING RECEIVED BINARY ELEMENTS TO AN INITIAL STAGE OF SAID SHIFT REGISTER, TIMING MEANS RESPONSIVE TO THE RECEPTION OF SAID START ELEMENT BY SAID RECEIVING MEANS FOR GENERATING A TIMING INTERVAL, MEANS RESPONSIVE TO SAID TIMING MEANS DURING SAID TIMING INTERVALS FOR APPLYING SHIFT PULSES TO SAID SHIFT REGISTER, A TRANSLATOR CIRCUIT HAVING A PLURALITY OF INPUT LEADS AND A PLURALITY OF OUTPUT LEADS, GATE MEANS FOR SELECTIVELY ENERGIZING EACH OF SAID TRANSLATOR CIRCUIT INPUT LEADS IN ACCORDANCE WITH THE CONDITIONS OF CORRESPONDING STAGES IN SAID SHIFT REGISTER, FIRST CIRCUIT MEANS ENABLED IN RESPONSE TO THE RECEPTION OF SAID STOP ELEMENT BY SAID RECEIVING MEANS AT THE TERMINATION OF SAID TIMING INTERVAL, SECOND CIRCUIT MEANS ENABLED IN THE ABSENCE OF SAID RECEPTION OF SAID STOP ELEMENT BY SAID RECEIVING MEANS AT THE TERMINATION OF SAID TIMING INTERVAL, MEANS JOINTLY RESPONSIVE TO THE SHIFTING OF SAID START ELEMENT TO A FINAL STAGE OF SAID SHIFT REGISTER AND SAID ENABLED FIRST CIRCUIT MEANS FOR ENABLING SAID GATE MEANS, MEANS JOINTLY RESPONSIVE TO THE SHIFTING OF SAID START ELEMENT TO SAID FINAL STAGE OF SAID SHIFT REGISTER AND SAID ENABLED SECOND CIRCUIT MEANS FOR DIRECTLY ENERGIZING SELECTED ONES OF SAID TRANSLATOR OUTPUT LEADS, AND MEANS FOR REMOVING SAID BINARY ELEMENTS FROM SAID SHIFT REGISTER, SAID REMOVING MEANS RENDERED OPERABLE BY ONE OF SAID FIRST AND SECOND ENABLED CIRCUIT MEANS.