Patent US3143484A successfully refreshed from Google Patents.
US3143484A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making plated circuit boards
Assignee: General Electric Co
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Filing: 1959-12-29
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Granted: 1964-08-04
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Expires: 1979-12-29
Abstract
No abstract record available.
Inventors
- 👤 Raymond G Olin
- 👤 Ralph W Richter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:24
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/22; H05K3/24; H05K3/241; H05K3/242; H05K3/10; H05K3/18; H05K3/181; H05K3/182; H05K3/184; H05K2203/00; H05K2203/15; H05K2203/1572; H05K2203/1581; H05K3/40; H05K3/42; H05K3/425; H05K3/426
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
153 words
A METHOD OF MAKING A PLATED CIRCUIT BOARD, COMPRISING THE STEPS OF PROVIDING A BOARD OF ELECTRICALLY IN SULATING MATERIAL DEVOID OF METAL LAMINATIONS ON THE SURFACES THEREOF, PROVIDING AT LEAST ONE HOLE THROUGH SAID BOARD AT EACH AREA THEREOF WHERE A PLATED CONDUCTOR IS DESIRED, APPLYING A RESIST TO THE FRONT SURFACE OF THE BOARD AT ALL AREAS EXCEPT WHERE PLATED CONDUCTORS ARE DESIRED, ELECTROLESS-PLATING CONDUCTIVE MATERIAL ONTO THE WALLS OF SAID HOLES AND ONTO BOTH SURFACES OF THE BOARD EXCEPT WHERE COVERED BY SAID RESIST, APPLYING A RESIST OVER THE ELECTROLESS-PALTED MATERIAL ON THE BACK SURFACE ONLY OF SAID BOARD, ELECTROPLATING CONDUCTIVE MATERIAL ONTO THE EXPOSED ELECTROLESS-PLATED AREAS BY MAKING A CURRENT CONNECTION THROUGH THE ELECTROLESS PLATING ON THE BACK SURFACE FO THE BOARD, AND REMOVING THE RESIST AND THE ELECTROLESS-PLATED MATERIAL FORM THE BACK SURFACE OF SAID BOARD TO SEVER ELECTRICAL CONNECTIONS THAT WERE USED FOR THE STEP OF ELECTROPLATING.
Claim 2
Independent Claim
153 words
A METHOD OF MAKING A PLATED CIRCUIT BOARD, COMPRISING THE STEPS OF PROVIDING A BOARD OF ELECTRICALLY IN SULATING MATERIAL DEVOID OF METAL LAMINATIONS ON THE SURFACES THEREOF, PROVIDING AT LEAST ONE HOLE THROUGH SAID BOARD AT EACH AREA THEREOF WHERE A PLATED CONDUCTOR IS DESIRED, APPLYING A RESIST TO THE FRONT SURFACE OF THE BOARD AT ALL AREAS EXCEPT WHERE PLATED CONDUCTORS ARE DESIRED, ELECTROLESS-PLATING CONDUCTIVE MATERIAL ONTO THE WALLS OF SAID HOLES AND ONTO BOTH SURFACES OF THE BOARD EXCEPT WHERE COVERED BY SAID RESIST, APPLYING A RESIST OVER THE ELECTROLESS-PALTED MATERIAL ON THE BACK SURFACE ONLY OF SAID BOARD, ELECTROPLATING CONDUCTIVE MATERIAL ONTO THE EXPOSED ELECTROLESS-PLATED AREAS BY MAKING A CURRENT CONNECTION THROUGH THE ELECTROLESS PLATING ON THE BACK SURFACE FO THE BOARD, AND REMOVING THE RESIST AND THE ELECTROLESS-PLATED MATERIAL FORM THE BACK SURFACE OF SAID BOARD TO SEVER ELECTRICAL CONNECTIONS THAT WERE USED FOR THE STEP OF ELECTROPLATING.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1967-08-04 | 1968-02-03 | 1968-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1971-08-04 | 1972-02-03 | 1972-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1975-08-04 | 1976-02-03 | 1976-08-04 | $7700.00 | Window Closed / Lapsed |