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Claim 1

IN A DATA PROCESSING DEVICE WHEREIN A PLURALITY OF INPUT-OUTPUT UNITS MAY TRANSFER DATA TO OR RECEIVE DATA FROM A CENTRAL PROCESSOR, THE DATA PROCESSING DEVICE HAVING A SCAN ELEMENT DISPOSED BETWEEN THE PLURALITY OF INPUT-OUTPUT UNITS AND THE CENTRAL PROCESSOR, THE SCAN ELEMENT HAVING AT LEAST FIRST, SECOND AND THIRD STATUS CHANNELS SERIALLY CONNECTED, A SOURCE OF OSCILLATOR PULSES CONNECTED TO THE FIRST STATUS CHANNEL, EACH INPUT-OUTPUT DEVICE HAVING MEANS TO SUPPLY STATUS SIGNALS, MEANS CONVEYING THE STATUS SIGNAL OF EACH INPUT-OUTPUT DEVICE TO A SEPARATE STATUS CHANNEL WITH STATUS SIGNALS FROM THE FASTEST INPUT-OUTPUT UNIT BEING CONNECTED TO THE FIRST STATUS CHANNEL AND THE STATUS SIGNALS OF SUCCEEDING SLOWER INPUTOUTPUT UNITS BEING CONNECTED TO SUCCEEDING STATUS CHANNELS IN THE SERIES, A COUNTER, A CONTROL CIRCUIT CONNECTED BETWEEN SAID SOURCE OF OSCILLATOR PULSES AND SAID SERIALLY CONNECTED STATUS CHANNELS WHICH NORMALLY PASSES OSCILLATOR PULSES TO THE STATUS CHANNELS AND SAID COUNTER, EACH STATUS CHANNEL HAVING AN OUTPUT CONDUCTOR CONNECTED TO SAID CONTROL CIRCUIT WHICH CONVEYS A SIGNAL TO THE CONTROL CIRCUIT WHICH OPERATES THE CONTROL CIRCUIT: (A) TO INHIBIT THE PASSAGE OF OSCILLATOR PULSES, (B) TO SET THE COUNTER TO A PREDETERMINED COUNT, AND (C) TO SUPPLY A CONTROL SIGNAL TO THE CENTRAL PROCESSOR WHEN ANY ONE OF THE STATUS CHANNELS IS READY TO TRANSFER DATA TO OR RECEIVE DATA FROM THE CENTRAL PROCESSOR, MEANS COUPLED BETWEEN THE COUNTER AND SAID CONTROL CIRCUIT WHICH INHIBITS THE OCCURENCE OF OPERATIVE SIGNALS ON SAID OUTPUT CONDUCTOR OF EACH STATUS CHANNEL UNTIL SAID COUNTER REACHES A GIVEN COUNT WHICH DIFFERS FROM SAID PREDETERMINED COUNT, SAID CENTRAL PROCESSOR INCLUDING MEANS FOR SUPPLYING A SIGNAL TO THE CONTROL CIRCUIT WHICH OPERATES THE CONTROL CIRCUIT TO PASS OSCILLATOR PULSES WHEN A TRANSFER OF DATA TO OR FROM THE CENTRAL PROCESSOR IS COMPLETED, WHEREBY THE FIRST INPUT-OUTPUT UNIT IS INTERROGATED FIRST BY EACH OSCILLATOR PULSE FROM SAID CONTROL CIRCUIT AND IS GIVEN PRECEDENCE OVER THE SECOND AND SUBSEQUENT INPUT-OUTPUT UNITS, THE SECOND INPUT-OUTPUT UNIT IS INTERROGATED SECOND BY EACH OSCILLATOR PULSE FROM SAID CONTROL CIRCUIT AND IS GIVEN PRECEDENCE OVER THE THIRD AND ANY SUBSEQUENT INPUT-OUTPUT UNITS, ET CETERA, AND ANY INPUT-OUTPUT UNIT WHICH IS READY TO TRANSFER OR RECIEVE DATA MUST WAIT UNTIL SAID COUNTER REACHES SAID GIVEN COUNT.