Patent EP0472941A2 successfully refreshed from Google Patents.
EP0472941A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
VHF/UHF plasma process for use in forming integrated circuit structures on semiconductor wafers
Assignee: Applied Materials Inc
•
Filing: 1991-07-31
•
Granted: —
•
Expires: 2011-07-31
Abstract
Abstract A method of fabricating integrated circuit structures on semiconductor wafers using a plasma-assisted process is disclosed wherein the plasma is generated by a VHF/UHF power source at a frequency ranging from about 50 to about 800 MHz. Low pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out within a pressure range not exceeding about 500 milliTorr; with a ratio of anode to cathode area of from about 2:1 to about 20:1, and an electrode spacing of from about 5 cm. to about 30 cm. High pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out with a pressure ranging from over 500 milliTorr up to 50 Torr or higher; with an anode to cathode electrode spacing of less than about 5 cm. By carrying out plasma-assisted processes using plasma operated within a range of from about 50 to about 800 MHz, the electrode sheath voltages are maintained sufficiently low, so as to avoid damage to structures on the wafer, yet sufficiently high to preferably permit initiation of the processes without the need for supplemental power sources. Operating in this frequency range may also result in reduction or elimination of microloading effects.
Inventors
- 👤 Kenneth S. Collins
- 👤 Craig A. Roderick
- 👤 Chan-Lon Yang
- 👤 David N. K. Wang
- 👤 Dan Maydan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 10:56
CPC Classifications
H; H01; H01J; H01J37/00; H01J37/32; H01J37/32009; H01J37/32082; H01J37/32174; C; C23; C23C; C23C16/00; C23C16/44; C23C16/50; C23C16/505; C23C16/509; H01J37/32091
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
56 words
A process for fabricating integrated circuit devices on semiconductor wafers in a vacuum chamber containing an electrode upon which a semiconductor wafer is mounted which comprises maintaining a plasma in said chamber energized by one or more power sources connected to said electrode and operated within a frequency range of from 50 MHz to 800 MHz.
Claim 2
Dependent Claim
25 words
The process of claim 1, wherein said power source is operated at a power density ranging from 10 to 76 watts/inch² * of wafer area.
Claim 3
Dependent Claim
30 words
The process of claim 1 or 2, wherein process is carried out in combination with the use of auxiliary magnets arranged around the exterior of said chamber for magnetic enhancement.
Claim 4
Dependent Claim
30 words
The process of one of the preceding claims, wherein said plasma is also coupled to another power source operated outside the frequency range of from 50 MHz to 800 MHz.
Claim 5
Dependent Claim
85 words
A plasma-assisted RIE process for etching materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using a power source having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 10 to 76 watts/inch² of wafer area in a vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from 2 to 500 milliTorr. **
Claim 6
Dependent Claim
34 words
The process of claim 5 wherein said anode and cathode electrodes have a ratio of anode to cathode area of at least about 2:1 and an electrode spacing of about 5 cm or more.
Claim 7
Dependent Claim
24 words
The process of claim 5 or 6, wherein said anode and cathode electrodes have an electrode spacing ranging from 5 cm to 30 cm.
Claim 8
Dependent Claim
21 words
The process of one of claims 5 to 7, wherein said pressure in said chamber ranges from 20 to 200 milliTorr.
Claim 9
Dependent Claim
22 words
The process of one of claims 5 to 8, wherein said power density ranges from 45 to 56 watts/inch² of wafer area.
Claim 10
Dependent Claim
30 words
The process of one of claims 5 to 9 wherein said RIE process comprises a process for etching silicon oxide at an etch rate of from 0.3 to 0.75 µm/minute.
Claim 11
Dependent Claim
22 words
The process of claim 10, wherein said power source is operated within a frequency range of from 100 MHz to 250 MHz.
Claim 12
Dependent Claim
45 words
The process of one of claims 5 to 11, which further comprises flowing a source of fluorine, an optional source of hydrogen, a source of carbon, an optional source of oxygen, and an optional inert gas through said chamber while said plasma is ignited therein.
Claim 13
Dependent Claim
74 words
The process of claim 12 wherein said RIE process comprises a selective process for etching silicon oxide in preference to polysilicon or photoresist wherein the atomic ratio of carbon to fluorine ranges from 0.1:1 to 2:1 and the atomic ratio of hydrogen present to fluorine ranges from 0.1:1 to 0.5:1 to obtain a ratio of silicon oxide etch (thickness) rate to polysilicon or photoresist etch (thickness) rate of from about 2:1 to over 30:1.
Claim 14
Dependent Claim
31 words
The process of one of claims 5 to 8 wherein said RIE process comprises a process for etching polysilicon and/or aluminum at an etch rate of from 0.2 to 1.0 µm/minute.
Claim 15
Dependent Claim
29 words
The process of claim 14 wherein said power source is operated within a frequency range of from 100 MHz to 800 MHz, preferably from 150 MHz to 600 MHz.
Claim 16
Dependent Claim
20 words
The process of claim 14 or 15 wherein said power density ranges from 20 to 40 watts/inch² of wafer area.
Claim 17
Dependent Claim
30 words
The process of one of claims 14 to 16 which further comprises flowing a chlorine-containing gas and an optional inert gas through said chamber while said plasma is ignited therein.
Claim 18
Dependent Claim
89 words
A plasma-assisted high pressue process for etching materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using one or more power sources having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 15 to 76 watts/inch² of wafer area in a vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of over 500 milliTorr to about 50 Torr.
Claim 19
Dependent Claim
28 words
The process of claim 18 wherein said anode and cathode electrodes have an electrode spacing of less than 5 cm, preferably ranging from 0.2 cm to 5 cm.
Claim 20
Dependent Claim
31 words
The process of claim 18 or 19 wherein said high pressure plasma etching process comprises a process for etching silicon oxide at an etch rate of from 0.2 to 1.0 µm/minute.
Claim 21
Dependent Claim
25 words
The process of claim 20 wherein said high pressure plasma etching process is operated within a pressure range of from 1 Torr to 20 Torr.
Claim 22
Dependent Claim
23 words
The process of claim 20 or 21 wherein the power is maintained at a power density level ranging from 30 to 50 watts/inch².
Claim 23
Dependent Claim
37 words
The process of one of claims 20 to 22 which further comprises flowing a source of fluorine, a source of carbon, an optional source of hydrogen, and an optional inert gas through said chamber during said etch.
Claim 24
Dependent Claim
80 words
The process of one of claims 20 to 23 wherein said high pressure plasma process comprises a selective process for etching silicon oxide in preference to polysilicon or photoresist wherein the atomic ratio of carbon to fluorine ranges from 0.1:1 to 2:1 and the atomic ratio of hydrogen present to fluorine ranges from 0.1:1 to 0.5:1 to obtain a ratio of silicon oxide etch (thickness) rate to polysilicon or photoresist etch (thickness) rate of from about 2:1 to over 30:1.
Claim 25
Dependent Claim
32 words
The process of claim 18 or 19 wherein said high pressure plasma etching process comprises a process for etching polysilicon and/or aluminum at an etch rate of from 0.2 to 1.0 µm/minute.
Claim 26
Dependent Claim
25 words
The process of claim 25 wherein said high pressure plasma etching process is operated within a pressure range of from 1 Torr to 20 Torr.
Claim 27
Dependent Claim
23 words
The process of claim 25 or 26 wherein the power is maintained at a power density level ranging from 20 to 40 watts/inch².
Claim 28
Dependent Claim
28 words
The process of one of claims 25 to 27 which further comprises flowing a source of chlorine and an optional inert gas through said chamber during said etch.
Claim 29
Dependent Claim
88 words
A plasma-assisted low pressure CVD process for depositing materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using one or more power sources having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 10 to 76 watts/inch² of wafer area in a vacuum deposition chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of from 2 to 500 milliTorr.
Claim 30
Dependent Claim
32 words
The process of claim 29 wherein said anode and cathode electrodes have an anode to cathode electrode spacing of about 5 cm or more, preferably ranging from 5 cm to 30 cm.
Claim 31
Dependent Claim
30 words
The process of claim 29 or 30 wherein said low pressure CVD process comprises a process for depositing silicon oxide at a deposition rate of from 0.1 to 1.5 µm/minute.
Claim 32
Dependent Claim
22 words
The process of claim 31 wherein said power source is operated within a frequency range of from 100 MHz to 250 MHz.
Claim 33
Dependent Claim
19 words
The process of claim 31 or 32 wherein said pressure in said chamber ranges from 20 to 200 milliTorr.
Claim 34
Dependent Claim
22 words
The process of one of claims 31 to 33 wherein said power density ranges from 45 to 56 watts/inch² of wafer area.
Claim 35
Dependent Claim
39 words
The process of one of claims 31 to 34 which further comprises flowing one or more sources of silicon, one or more sources of oxygen, and an optional inert gas through said chamber while said plasma is ignited therein.
Claim 36
Dependent Claim
30 words
The process of claim 29 or 30 wherein said low pressure CVD process comprises a process for depositing silicon nitride at a deposition rate of from 0.1 to 1.5 µm/minute.
Claim 37
Dependent Claim
22 words
The process of claim 36 wherein said power source is operated within a frequency range of from 100 MHz to 250 MHz.
Claim 38
Dependent Claim
25 words
The process of claim 36 or 37 wherein said pressure in said chamber ranges from 2 to 500 milliTorr, preferably from 20 to 200 milliTorr.
Claim 39
Dependent Claim
31 words
The process of one of claims 36 to 38 wherein said power density ranges from 30 to 76 watts/inch² of wafer area, preferably from 45 to 56 watts/inch² of wafer area.
Claim 40
Dependent Claim
44 words
The process of one of claims 36 to 39 which further comprises flowing one or more sources of silicon, one or more sources of nitrogen, an optional source of hydrogen, and an optional inert gas through said chamber while said plasma is ignited there.
Claim 41
Dependent Claim
92 words
A plasma-assisted high pressure CVD conformal isotropic process for depositing materials used in the fabrication of integrated circuit devices on semiconductor wafers which comprises maintaining a plasma using one or more power sources having a frequency range of from 50 MHz up to 800 MHz and maintained at a power density level ranging from 10 to 38 watts/inch² of wafer area in a vacuum etching chamber containing an anode and a wafer mounted on a cathode and maintained at a pressure within a range of over 500 milliTorr to about 50 Torr.
Claim 42
Dependent Claim
31 words
The process of claim 41 wherein said anode and cathode electrodes have an anode to cathode electrode spacing of less than 5 cm, preferably ranging from 0.2 cm to 5 cm.
Claim 43
Dependent Claim
32 words
The process of claim 41 or 42 wherein said plasma-assisted high pressure conformal isotropic deposition process comprises a process for depositing silicon oxide at a deposition rate of from 0.5 to 1.0µm/minute.
Claim 44
Dependent Claim
35 words
The process of one of claims 41 to 43 wherein said process further comprises flowing one or more sources of silicon, one or more sources of oxygen, and an optional inert gas through the chamber.
Claim 45
Dependent Claim
21 words
The process of claim 44 which further comprises maintaining a pressure in said chamber ranging from 1 Torr to 20 Torr.
Claim 46
Dependent Claim
35 words
The process of one of claims 41 or 42 wherein said plasma-assisted high pressure conformal isotropic deposition process comprises a process for depositing silicon nitride at a deposition rate of from 0.5 to 1.0 µm/minute.
Claim 47
Dependent Claim
36 words
The process of claim 46 wherein said process further comprises flowing one or more sources of silicon, one or more sources of nitrogen, an optional source of hydrogen, and an optional inert gas through the chamber.
Claim 48
Dependent Claim
23 words
The process of claim 46 or 47 which further comprises maintaining a pressure in said chamber ranging from 1 Torr to 20 Torr.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.