Patent EP0426386A2 successfully refreshed from Google Patents.
EP0426386A2
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EP
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Data destination facility
Assignee: Compaq Computer Corp
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Filing: 1990-10-26
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Granted: —
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Expires: 2010-10-26
Abstract
Abstract A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module (58) connected to a memory system. A RAM (126) is addressed by the system address lines defining 128 kbyte blocks, with the output data (TA, RASEN*) providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module (58). Various other parameters such as write protect status (HWP) and memory location (HLOCMEM*) are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.
Inventors
- 👤 John S. Thayer
- 👤 Dale J. Mayer
- 👤 John A. Landry
- 👤 Javier F. Izquierdo
- 👤 Paul R. Culley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 19:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
190 words
A memory accessing system for use in a computer system having an address bus (120) for communication of address values, a data bus (44/130) for communication of data and a control bus for communication of status and timing signals, the system comprising: at least one memory module (58) containing memory having data inputs and outputs coupled to the data bus and having address line and control inputs; means (62-68) for interfacing address and control signals to each of said memory modules, said interfacing means having enable signal inputs (RASEN*) for selecting the desired module; a plurality of address line inputs (HA), a portion of which are coupled to the address bus; control signal inputs connected to the control bus; and address line outputs which are connected to said memory module address line inputs and control signal outputs connected to said memory module control inputs; and memory selection random access memory (126) having address (HA) inputs which are coupled to the address bus, data inputs coupled to the data bus and data outputs (TA, RASEN*) coupled to said interfacing means enable signal inputs and a portion of said address line inputs.
Claim 2
Dependent Claim
190 words
A memory accessing system for use in a computer system having an address bus (120) for communication of address values, a data bus (44/130) for communication of data and a control bus for communication of status and timing signals, the system comprising: at least one memory module (58) containing memory having data inputs and outputs coupled to the data bus and having address line and control inputs; means (62-68) for interfacing address and control signals to each of said memory modules, said interfacing means having enable signal inputs (RASEN*) for selecting the desired module; a plurality of address line inputs (HA), a portion of which are coupled to the address bus; control signal inputs connected to the control bus; and address line outputs which are connected to said memory module address line inputs and control signal outputs connected to said memory module control inputs; and memory selection random access memory (126) having address (HA) inputs which are coupled to the address bus, data inputs coupled to the data bus and data outputs (TA, RASEN*) coupled to said interfacing means enable signal inputs and a portion of said address line inputs.
Claim 3
Dependent Claim
22 words
The memory accessing system of claim 1, further comprising means (122,124) for programming data values into said memory selection random access memory.
Claim 4
Dependent Claim
36 words
The memory accessing system of claim 2, wherein said programming means (122) includes means for setting a programming mode and means (122) for storing data values to be provided to said memory selection random access memory.
Claim 5
Dependent Claim
37 words
The memory accessing system of claim 3, wherein said programming means further includes means (124) for causing said stored data value to be strobed into said memory selection random access memory during a memory space write operation.
Claim 6
Dependent Claim
33 words
The memory accessing system of claim 4, wherein said data value strobe means includes means (124) for determining the value of an address line on the address bus to enable data value storage.
Claim 7
Dependent Claim
23 words
The memory accessing system of claim 2, further comprising means for reading a data value contained in said memory selection random access memory.
Claim 8
Dependent Claim
34 words
The memory accessing system of claim 6, wherein said programming means includes means (122) for setting a programming mode and means (122) for storing data values provided by said memory selection random access memory.
Claim 9
Dependent Claim
42 words
The memory accessing system of claim 7, wherein said programming means further includes means (124) for causing the data value provided said memory selection random access memory to be strobed in said data value storing means during a memory space write operation.
Claim 10
Dependent Claim
32 words
The memory accessing system of claim 8, wherein said data value strobe means includes means (124) for determining the value of an-address line on the address bus to enable data value storage.
Claim 11
Dependent Claim
51 words
The memory accessing system of claim 1, wherein said interfacing means (62) includes a write protect input which is used to disable write operations to said memory modules and where in said memory selection random access memory (126) has a data (HWP) output connected to said interfacing means write protect input.
Claim 12
Dependent Claim
49 words
The memory accessing system of claim 1, wherein said interfacing means (62) includes a local memory input which is used to disable operation of said memory modules and wherein said memory selection random access memory (126) has a data output (HLOCMEM*) connected to said interfacing means local memory input.
References Cited (Backward Citations)
No citation records indexed.
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