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EP0263312A2
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Semiconductor memory device with a self-testing function
Assignee: Toshiba Corp
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Filing: 1987-09-08
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Granted: —
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Expires: 2007-09-08
Abstract
Abstract A semiconductor memory device comprises a self-test circuit (17, 18, 19, 20). The self-test circuit starts to operate in response to a control signal. The self-test circuit controls the operation of data writing and data reading so that data are written into the memory cells in the memory cell array and read out the data from the memory cells. The self-test circuit checks whether or not an error is contained in the read data by comparing the read data with the write data.
Inventors
- 👤 Tohru C/O Patent Division Furuyama
- 👤 Kenji C/O Patent Division Natori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 15:18
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/20; G11C29/44; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/267
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
132 words
A semiconductor memory device comprising: a memory cell array (10) including a plurality of memory cells; memory cells select means (11, 13, 16) for selecting a memory cell in said memory cell array (10); and data write means (14) for writing data into the memory cell selected by said memory cell select means; data read out means (12, 14) for reading out the data from the memory cell selected by said memory cell select means; characterized by further comprising: self-test means (17, 18, 19, 20) for operating said data write and read means in responsive to a control signai, writing predetermined data into the memory cells in said memory cell array (10), reading out the data from said memory cells, and checking if an error is contained in the read out data.
Claim 2
Dependent Claim
132 words
A semiconductor memory device comprising: a memory cell array (10) including a plurality of memory cells; memory cells select means (11, 13, 16) for selecting a memory cell in said memory cell array (10); and data write means (14) for writing data into the memory cell selected by said memory cell select means; data read out means (12, 14) for reading out the data from the memory cell selected by said memory cell select means; characterized by further comprising: self-test means (17, 18, 19, 20) for operating said data write and read means in responsive to a control signai, writing predetermined data into the memory cells in said memory cell array (10), reading out the data from said memory cells, and checking if an error is contained in the read out data.
Claim 3
Dependent Claim
118 words
The semiconductor memory device according to claim 1, characterized in that said self-test means (17, 18. 19, 20) includes an address counter (17) for generating an address signal to specify any of the memory cells in said memory cell array, a write data generation circuit (19) for generating the data to be written into said memory cells, a data comparing circuit (20) for comparing the same data as that stored into said memory cells with the data - read out of said memory cells, and a control circuit (18) for operating said address counter, said write data generation circuit, and said data comparing circuit in response to said control signal, and for controlling the operation of said circuits.
Claim 4
Dependent Claim
60 words
The semiconductor memory device according to claim 2. characterized in that said address counter (17) and said write data generation circuit (19) are comprised of a plurality of counters coupled in series, and said write data generation circuit is couoled with the output signal from that counter of said counters forming said address counter. which provides the most significant bit.
Claim 5
Dependent Claim
42 words
The semiconductor memory device according to claim 2. characterized in that the memory cells in said memory cell array (10) are dynamic cells, and some of the counters forming said address counter generate an address signal used for refreshing the memory cells.
Claim 6
Dependent Claim
30 words
The semiconductor memory device according to claim 1. characterized in that said control signal is supplied from an external terminal specially provided, which is not used in the normal operation.
Claim 7
Dependent Claim
39 words
The semiconductor memory device according to claim 1, characterized in that said control signal has a potential which is supplied to an external terminal used in the normal operation, and is different from those used in the normal operation.
Claim 8
Dependent Claim
37 words
The semiconductor memory device according to claim 1, characterized in that said self-test means (17, 18. 19. 20) is provided with a failure signal output means (20) for outputting a signal indicative of detection of error data.
Claim 9
Dependent Claim
27 words
The semiconductor memory device according to claim 1, characterized in that the checking cycle of said self-test means (17, 18, 19, 20) is controlled by timer means.
Claim 10
Dependent Claim
28 words
The semiconductor memory device according to claim 1, characterized in that said address counter (17) includes a plurality of R-S flip-flop (30. to 30 18 ) serially connec:ec.
Claim 11
Dependent Claim
28 words
The semiconductor memory device according to claim 1, characterized in that said address counter (17) includes a plurality of frequency divider (30, to 30 18 ) serially connected.
Claim 12
Dependent Claim
52 words
The semiconductor memory device according to claim 1, characterized by further comprising operation control means (21) for detecting that predetermined signals are input to a plurality of external terminals used in the normal operation in a predetermined order and predetermined levels, and for providing said control signal for operating said self-test means.
Claim 13
Dependent Claim
29 words
The semiconductor memory device according to claim 11, characterized in that the predetermined signal detected by said operation control means (21) contains some or all of the address signals.
Claim 14
Dependent Claim
48 words
The semiconductor memory device accord-. ing to claim 11. characterized in that some lower order digits of said address counter (17) are used as a row address to address said memory cells. and some higher order digits are used as a column address to address said memory cells.
Claim 15
Dependent Claim
64 words
The semiconductor memory device according to claim 11. charactenzed in that said operation control means (21) detects a column address strobe signal ( CAS ) and a row address strobe signal ( RAS ). which are input via said plural external terminals, and operates said self-test means when detecting that the column address strobe signal is input prior to the row address strobe signal.
Claim 16
Dependent Claim
81 words
The semiconductor memory device according to claim 11, characterized in that said operation control means (21) detects a column address strobe signal ( CAS ), a row address strobe signal ( RAS ), and a write enable signal ( WE ), which are input via said plural external terminals, and operates said self-test means in response to the level of the write enable signal when detecting that the column address strobe signal is input prior to the row address strobe signal.
Claim 17
Dependent Claim
96 words
The semiconductor memory device according to claim 11, characterized in that said operation control means (21) detects a column address strobe signal ( CAS ). a row address strobe signal ( RAS ), a write enable signal ( WE ), and an external address signal, which are input via said plural external terminals, and operates said self-test means when detecting that the column address strobe signal is input prior to the row address strobe signal, and the write enable signal is in a predetermined level, and the bits of the external address signal have predetermined levels.
References Cited (Backward Citations)
No citation records indexed.
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