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EP0108255A1
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Self-testing circuitry for a combinatorial and sequential logic circuit
Assignee: International Business Machines Corp
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Filing: 1983-10-05
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Granted: —
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Expires: 2003-10-05
Abstract
Abstract The LSSD scan paths (16) of each logic circuit chip (10) on a circuit module (12) are connected to additional test circuit chips (10t) on the same module. The test chips contain a random signal generator (22) and data compression circuit (24) to perform random stimuli signature generation and also contain switching circuits to connect the scan paths of the chips in parallel between different stages of the random signal generator (22) and the data compression means (24) and to disconnect the scan paths from the signal generator and data compression circuitry and arrange them serially in a single scan path to perform other tests.
Inventors
- 👤 William Howard Mcanney
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 11:32
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
177 words
Self-testing circuitry in a combinatorial and sequential logic circuit with memory circuits (16) on individual logic units (10), the memory circuits, when coupled together, forming a shift register to provide a scan path (18) for testing associated logic circuits and, when uncoupled, disabling the scan path while the logic circuits are performing their designed logic functions, the self-testing circuitry including a multistage generator means (22) to generate testing sequences for the self-testing and a multistage data compression means (24) to compress the responses of the logic circuits, and being characterized in that it comprises test circuit unit means (10t) containing the generator means (22) and the data compression means (24, circuit means (18, 19) coupling the scan paths (16) of the logic units (10) to the test circuit unit means and, logic means (30, 32, 46, 50) for coupling the scan paths (18 i , 18 j+1 ,...18n) of the logic units (10., 10 j+1 ,...10n) in a plurality of parallel paths between different stages of the multistage generator (22) and the multistage data compression means (24).
Claim 2
Dependent Claim
177 words
Self-testing circuitry in a combinatorial and sequential logic circuit with memory circuits (16) on individual logic units (10), the memory circuits, when coupled together, forming a shift register to provide a scan path (18) for testing associated logic circuits and, when uncoupled, disabling the scan path while the logic circuits are performing their designed logic functions, the self-testing circuitry including a multistage generator means (22) to generate testing sequences for the self-testing and a multistage data compression means (24) to compress the responses of the logic circuits, and being characterized in that it comprises test circuit unit means (10t) containing the generator means (22) and the data compression means (24, circuit means (18, 19) coupling the scan paths (16) of the logic units (10) to the test circuit unit means and, logic means (30, 32, 46, 50) for coupling the scan paths (18 i , 18 j+1 ,...18n) of the logic units (10., 10 j+1 ,...10n) in a plurality of parallel paths between different stages of the multistage generator (22) and the multistage data compression means (24).
Claim 3
Dependent Claim
31 words
Circuitry as in claim 1, including means (30) for connecting the parallel paths into a single scan path including the scan paths of all logic units arranged on a module (12).
Claim 4
Dependent Claim
43 words
Circuitry as in claim 1, wherein the stages of the multistage random signal generator (22) and the multistage data compression means (24) and the memory circuits (16) can all be operated to shift data between them using the same set of shift pulses.
References Cited (Backward Citations)
No citation records indexed.
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