USRE28633E
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state digital-to-analog converter
Assignee: —
•
Filing: 1974-11-18
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Granted: 1975-11-25
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Expires: 1994-11-18
Abstract
Abstract A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such ''''quad'''' switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.
Inventors
No inventors recorded.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10D99/00; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
135 words
An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate; switch control means operable by a digital input for selectively activating any of said transistors to pass current therethrough; circuit means for said transistors to set different levels of current therethrough according to a predetermined weighting pattern such that the sum of the currents produced by the activated transistors represents an analog output in accordance with the required digital-to-analog relationship; each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern, to provide uniform current density in said transistors when activated; and means for summing the currents flowing through the transistors activated by said switch means so as to provide said analog output.
Claim 2
Dependent Claim
135 words
An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate; switch control means operable by a digital input for selectively activating any of said transistors to pass current therethrough; circuit means for said transistors to set different levels of current therethrough according to a predetermined weighting pattern such that the sum of the currents produced by the activated transistors represents an analog output in accordance with the required digital-to-analog relationship; each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern, to provide uniform current density in said transistors when activated; and means for summing the currents flowing through the transistors activated by said switch means so as to provide said analog output.
Claim 3
Dependent Claim
31 words
A converter as in claim 1, wherein said transistors are provided with different numbers of emitters proportional to the magnitude of current to be passed, said emitters all having equal areas.
Claim 4
Dependent Claim
48 words
A converter as in claim 1, including a second substrate having a plurality of resistors formed thereon; and means interconnecting each of said transistors with a respective one of said resistors to control the current through each transistor in accordance with the ohmic resistance of the associated resistor.
Claim 5
Dependent Claim
26 words
A converter as in claim 1, wherein said substrate is formed with four switching transistors the emitters of which have areas in the ratios of 1:2:4:8.
Claim 6
Dependent Claim
59 words
Apparatus as in claim 1, wherein said substrate has said plurality of transistors diffused therein to serve as separate current sources corresponding to respective bits of a digital input signal; each of said transistors comprising an emitter, a base and a collector; the areas of the respective emitters for said transistors differing in accordance with a binary weighting pattern.
Claim 7
Dependent Claim
34 words
Apparatus as in claim 5, wherein each of said transistors has a number of separate equal-size emitter sections, with the number of sections in each case being in accordance with said binary weighting pattern.
Claim 8
Dependent Claim
27 words
Apparatus as in claim 5, wherein the size of the base segment for each transistor is at least approximately proportional to the area of the corresponding emitter.
Claim 9
Dependent Claim
21 words
Apparatus as in claim 7, wherein said substrate is formed with a single collector segment common to all of said transistors.
Claim 10
Dependent Claim
124 words
An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate; an output line; switch control means operable by a digital input for selectively activating any of said transistors to pass the current thereof through said output line; circuit means for said transistors to set different levels of current through each transistor according to a predetermined weighting pattern such that the sum of the currents produced in said output line by the selected transistors represents an analog output corresponding to said digital input; each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern to provide uniform current density in the activated transistors.
Claim 11
Dependent Claim
124 words
An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate; an output line; switch control means operable by a digital input for selectively activating any of said transistors to pass the current thereof through said output line; circuit means for said transistors to set different levels of current through each transistor according to a predetermined weighting pattern such that the sum of the currents produced in said output line by the selected transistors represents an analog output corresponding to said digital input; each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern to provide uniform current density in the activated transistors.
Claim 12
Dependent Claim
23 words
Apparatus as in claim 9, wherein the emitter area of each of said transistors is proportional to the particular current level assigned thereto.
Claim 13
Dependent Claim
139 words
An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate each adapted to conduct current; an output line; means operable by a digital input signal for developing in said output line a flow of current representing the summation of the currents of any of said transistors selected in accordance with said digital input signal; circuit means for said transistors to set different levels of current therethrough according to a predetermined weighting pattern such that the sum of the currents produced in said output line by the transistors represents an analog output signal corresponding to said digital input signal; each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern to provide uniform current density in said transistors.
Claim 14
Dependent Claim
139 words
An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate each adapted to conduct current; an output line; means operable by a digital input signal for developing in said output line a flow of current representing the summation of the currents of any of said transistors selected in accordance with said digital input signal; circuit means for said transistors to set different levels of current therethrough according to a predetermined weighting pattern such that the sum of the currents produced in said output line by the transistors represents an analog output signal corresponding to said digital input signal; each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern to provide uniform current density in said transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-24 | 1979-05-26 | 1979-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-24 | 1983-05-26 | 1983-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-24 | 1987-05-26 | 1987-11-25 | $7700.00 | Window Closed / Lapsed |