US6006739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
Assignee: Micron Technology Inc
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Filing: 1999-03-17
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Granted: 1999-12-28
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Expires: 2019-03-17
Abstract
Abstract A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
Inventors
- 👤 Salman Akram
- 👤 Derek J. Gochnour
- 👤 Michael E. Hess
- 👤 David R. Hembree
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:57
CPC Classifications
B; B28; B28D; B28D5/00; B28D5/02; B28D5/022; B28D5/024; B28D5/029; Y; Y10; Y10T; Y10T83/00; Y10T83/02; Y10T83/0207; Y10T83/0215; Y10T83/0222; Y10T83/0333; Y10T83/0363; Y10T83/04; Y10T83/0524; Y10T83/768; Y10T83/7809; Y10T83/7868
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
86 words
A method of sawing a semiconductor substrate, comprising: making a first linear cut at least partially through a first portion of said substrate; making a second linear cut at least partially through a second portion of said substrate, said second cut being laterally spaced a distance from said first cut; and making a third linear cut at least partially through a third portion of said substrate, said third cut being spaced differently from said second cut than said second cut is spaced from said first cut.
Claim 2
Independent Claim
86 words
A method of sawing a semiconductor substrate, comprising: making a first linear cut at least partially through a first portion of said substrate; making a second linear cut at least partially through a second portion of said substrate, said second cut being laterally spaced a distance from said first cut; and making a third linear cut at least partially through a third portion of said substrate, said third cut being spaced differently from said second cut than said second cut is spaced from said first cut.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein said third cut is made at a greater distance from said second cut than said second cut is made from said first cut.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said first, second and third cuts effect scribe lines on a surface of said substrate.
Claim 5
Dependent Claim
20 words
The method of claim 3, further including cutting substantially through said substrate along said scribe lines with subsequent aligned cuts.
Claim 6
Dependent Claim
35 words
The method of claim 1, wherein said first and second cuts are made at substantially the same time and said third cut is made at a different time relative to said first and second cuts.
Claim 7
Dependent Claim
28 words
The method of claim 1, further including repeating a sequence of said first, second and third cuts across at least a portion of a surface of said substrate.
Claim 8
Dependent Claim
36 words
The method of claim 6, further including rotating said substrate substantially 90° and repeating at least one sequence of said first, second and third cuts across at least a portion of the surface of said substrate.
Claim 9
Dependent Claim
21 words
The method of claim 1, further including further varying spacing between said third cut and at least one additional linear cut.
Claim 10
Independent Claim
85 words
A method of dicing a semiconductor substrate, comprising: substantially severing the semiconductor substrate at a first substantially linear location; substantially severing the semiconductor substrate at a second substantially linear location substantially parallel to said first substantially linear location and spaced a first distance apart from said first substantially linear location; and substantially severing the semiconductor substrate at a third substantially linear location substantially parallel to said first substantially linear location and spaced a different distance from said second substantially linear location than said first distance.
Claim 11
Independent Claim
85 words
A method of dicing a semiconductor substrate, comprising: substantially severing the semiconductor substrate at a first substantially linear location; substantially severing the semiconductor substrate at a second substantially linear location substantially parallel to said first substantially linear location and spaced a first distance apart from said first substantially linear location; and substantially severing the semiconductor substrate at a third substantially linear location substantially parallel to said first substantially linear location and spaced a different distance from said second substantially linear location than said first distance.
Claim 12
Dependent Claim
17 words
The method of claim 9, further comprising forming a scribe line at said first substantially linear location.
Claim 13
Dependent Claim
24 words
The method of claim 10, wherein said forming said scribe line precedes said substantially severing the semiconductor substrate at said first substantially linear location.
Claim 14
Dependent Claim
17 words
The method of claim 9, further comprising forming a scribe line at said second substantially linear location.
Claim 15
Dependent Claim
24 words
The method of claim 12, wherein said forming said scribe line precedes said substantially severing the semiconductor substrate at said second substantially linear location.
Claim 16
Dependent Claim
17 words
The method of claim 9, further comprising forming a scribe line at said third substantially linear location.
Claim 17
Dependent Claim
24 words
The method of claim 14, wherein said forming said scribe line precedes said substantially severing the semiconductor substrate at said third substantially linear location.
Claim 18
Dependent Claim
34 words
The method of claim 9, wherein said substantially severing the semiconductor device at said first substantially linear location and said substantially severing the semiconductor device at said second substantially linear location occur substantially simultaneously.
Claim 19
Dependent Claim
49 words
The method of claim 16, wherein said substantially severing the semiconductor device at said first substantially linear location and said substantially severing the semiconductor device at said second substantially linear location occur at a different time than said substantially severing the semiconductor device at said third substantially linear location.
Claim 20
Dependent Claim
30 words
The method of claim 17, wherein said substantially severing the semiconductor device at said third substantially linear location occurs independently of substantially severing the semiconductor device at any other location.
Claim 21
Dependent Claim
28 words
The method of claim 9, further comprising repeating a sequence of said substantially severing the semiconductor device at each of said first, second, and third substantially linear locations.
Claim 22
Dependent Claim
35 words
The method of claim 9, further comprising substantially severing the semiconductor device at another substantially linear location spaced a third distance apart from an adjacent one of said first, second, or third substantially linear locations.
References Cited (Backward Citations)
DE287869C
Cited
US2762954A
Cited
US2865082A
Cited
US3664389A
Cited
US3688815A
Cited
US3892156A
Cited
US4006656A
Cited
US3961547A
Cited
US4102227A
Cited
US4138304A
Cited
US4287256A
Cited
US4451972A
Cited
US4343662A
Cited
US4633847A
Cited
US4688540A
Cited
US4705016A
Cited
US4804641A
Cited
US4937653A
Cited
US5046392A
Cited
US5059899A
Cited
US5128282A
Cited
US5259149A
Cited
US5316559A
Cited
US5323150A
Cited
US5362681A
Cited
US5458034A
Cited
US5580831A
Cited
US5326428A
Cited
US5468541A
Cited
US5461008A
Cited
US5521125A
Cited
US5851845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |