Microprocessor power control system

Claim 1

A power control system for a microprocessor including in combination: a plurality of integer execution units and a plurality of floating point execution units connected in parallel to operate simultaneously between an input bus and an output bus in said microprocessor; an instruction dispatcher coupled through said input bus to said execution units for supplying instructions for execution by said execution units, wherein multiple instructions may be executed simultaneously by different ones of said execution units; a source of clock signals for operating said execution units; a plurality of normally enabled power control gates coupled between said source of clock signals and less than all of said integer execution units and less than all of said floating point execution units for normally passing clock signals to said execution units when the corresponding ones of said gates are enabled; and a source of gate control signals coupled with said gates for enabling and disabling said gates, whereby whenever said gates are disabled, clock pulses are not passed to said less than all of said execution units which then are not operated, thereby reducing power consumption of said microprocessor.