US5937318A
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US
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Monocrystalline three-dimensional integrated circuit
Assignee: Individual
•
Filing: 1991-05-24
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Granted: 1999-08-10
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Expires: 2011-05-24
Abstract
Abstract A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated. "Writing" on the growing crystal is done during crystal growth by methods that may include but not be limited to ion beams, laser beams, patterned light exposures, and physical masks. The interior volume of the fabrication apparatus is far cleaner and more highly controlled than that of a clean room. The apparatus is highly, replicated and is amenable to mass production. The product has unprecedented volumetric function density, and high performance stems from short signal paths, low parasitic loading, and 3-D architecture. High reliability stems from contamination-free fabrication, small signal-arrival skew, and generous noise margins. Economy stems from mass-produced factory apparatus, automatic IC manufacture, and high IC yield. Among the IC products are fast and efficient memories with equally fast and efficient error-correction abilities, crosstalk-free operational amplifiers, and highly paralleled and copiously interconnected neural networks.
Inventors
- 👤 Raymond M. Warner, Jr.
- 👤 Ronald D. Schrimpf
- 👤 Alfons Tuszynski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:39
CPC Classifications
H; H10; H10W; H10W15/00; H10D; H10D30/00; H10D30/80; H10D30/83; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/01
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
110 words
A method for fabricating an integrated-circuit monolith that is substantially monocrystalline and having parts that are substantially lattice-matched, said monolith being three-dimensional in the sense that it comprises two or more layers of circuitry, said method combining at least the following technologies: a. sputter deposition of a type-1 semiconductor material by using a type-1 semiconductor target; b. sputter deposition of a small amount of heavily doped type-2 semiconductor material by using a type-2 semiconductor target; c. diffusion in selected areas of the type-2 impurity by using incident patterned light; d. removal of type-2 impurity from nonselected areas by ion milling; and, e. rapid annealing by using general (unpatterned) incident light.
Claim 2
Independent Claim
110 words
A method for fabricating an integrated-circuit monolith that is substantially monocrystalline and having parts that are substantially lattice-matched, said monolith being three-dimensional in the sense that it comprises two or more layers of circuitry, said method combining at least the following technologies: a. sputter deposition of a type-1 semiconductor material by using a type-1 semiconductor target; b. sputter deposition of a small amount of heavily doped type-2 semiconductor material by using a type-2 semiconductor target; c. diffusion in selected areas of the type-2 impurity by using incident patterned light; d. removal of type-2 impurity from nonselected areas by ion milling; and, e. rapid annealing by using general (unpatterned) incident light.
Claim 3
Dependent Claim
66 words
Method of claim 1 wherein said monolith comprises at least one material from the following group: a. silicon; b. germanium; c. diamond; d. silicon carbide; e. aluminum antimonide; f. boron phosphide; g. gallium arsenide: h. gallium aluminum arsenide; i. gallium phosphide; j. indium phosphide; k. cadmium sulfide; l. cadmium selenide; m. cadmium telluride; n. zinc oxide; o. zinc sulfide; p. monocrystalline insulator; and, q. monocrystalline metal.
Claim 4
Dependent Claim
20 words
Method of claim 1 wherein at least one elemental target is substituted for at least one of the doped-semiconductor targets.
Claim 5
Dependent Claim
25 words
Method of claim 1 wherein the patterned incident light is provided by the combination of a mask, image-forming optics, and an intense, energetic light source.
Claim 6
Dependent Claim
26 words
Method of claim 1 wherein the patterned incident light is provided by the combination of an intense, energetic light source and an electronically controlled pattern generator.
Claim 7
Dependent Claim
15 words
Method of claim 1 wherein the patterned incident light is provided by a laser-holographic method.
Claim 8
Dependent Claim
10 words
Method of claim 1 carried out in a continuous manner.
Claim 9
Dependent Claim
10 words
Method of claim 1 carried out in a quasicontinuous manner.
Claim 10
Dependent Claim
10 words
Method of claim 1 carried out in a single apparatus.
Claim 11
Dependent Claim
20 words
Method of claim 1 carried out in a way that subjects the work in process to relatively small temperature excursions.
Claim 12
Dependent Claim
20 words
Method of claim 1 carried out in a way that subjects the work in process to relatively small pressure excursions.
Claim 13
Dependent Claim
23 words
Method of claim 1 wherein sputtering through a physical or shadow mask is substituted for light-stimulated impurity diffusion in order to accomplish patterning.
Claim 14
Dependent Claim
11 words
Method of claim 1 carried out repeatedly in a closed system.
Claim 15
Dependent Claim
11 words
Method of claim 1 carried through repeatedly in a single-pumpdown operation.
Claim 16
Dependent Claim
11 words
Method of claim 1 carried out repeatedly and comprising in-situ patterning.
Claim 17
Dependent Claim
22 words
Method of claim 1 carried out repeatedly and comprising patterning by means comprising a liquid-crystal display that serves as a pattern generator.
Claim 18
Dependent Claim
27 words
Method of claim 1 carried out repeatedly and subsumed in a procedure during which the crystal-growth surface remains substantially plane from start to finish of said procedure.
Claim 19
Dependent Claim
64 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern, said sequence of crystal-layer increments created in a manner such that their successive two-dimensional patterns intersect where desired, and through two-dimensional-pattern variations, do not intersect in other regions.
Claim 20
Dependent Claim
64 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern, said sequence of crystal-layer increments created in a manner such that their successive two-dimensional patterns intersect where desired, and through two-dimensional-pattern variations, do not intersect in other regions.
Claim 21
Dependent Claim
10 words
Method of claim 18 carried out in a quasicontinuous manner.
Claim 22
Dependent Claim
22 words
Method of claim 18 carried out in a way that subjects the work in process to relatively small temperature and pressure excursions.
Claim 23
Dependent Claim
10 words
Method of claim 18 carried out in a closed system.
Claim 24
Dependent Claim
10 words
Method of claim 18 carried through in a single-pumpdown operation.
Claim 25
Dependent Claim
7 words
Method of claim 18 comprising in-situ patterning.
Claim 26
Dependent Claim
18 words
Method of claim 18 comprising patterning by means comprising a liquid-crystal display that serves as a pattern generator.
Claim 27
Dependent Claim
19 words
Method of claim 18 during which the crystal-growth surface remains substantially plane from start to finish of said procedure.
Claim 28
Dependent Claim
10 words
Method of claim 18 carried out in a single system.
Claim 29
Dependent Claim
67 words
Method of claim 18 wherein said integrated circuit comprises at least one material from the following group: a. silicon; b. germanium; c. diamond; d. silicon carbide; e. aluminum antimonide; f. boron phosphide; g. gallium arsenide; h. gallium aluminum arsenide; i. gallium phosphide; j. indium phosphide; k. cadmium sulfide; l. cadmium selenide; m. cadmium telluride; n. zinc oxide; o. zinc sulfide; p. monocrystalline insulator; and, q. monocrystalline metal.
Claim 30
Dependent Claim
199 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern created by a procedure that comprises at least three of the following five steps: a. growth by sputter epitaxy of a lightly doped first layer of semiconductor material of a first conductivity type; b. growth by sputter epitaxy of a heavily doped second layer, thinner than said first layer, of the same semiconductor material and of a second conductivity type; c. localized diffusion in selected areas of the impurities present in the said second layer into the said first layer by causing patterned light of appreciable intensity to fall on the surface of the said second layer; d. uniform removal by ion milling of the said second layer, thus removing from nonselected areas essentially all of the impurities associated with the said second layer of a second conductivity type, while leaving these said impurities distributed through the thickness of the said first layer in the said selected areas; and, e. thermal annealing of the grown crystal-layer increment by using unpatterned (uniform) incident light.
Claim 31
Dependent Claim
199 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern created by a procedure that comprises at least three of the following five steps: a. growth by sputter epitaxy of a lightly doped first layer of semiconductor material of a first conductivity type; b. growth by sputter epitaxy of a heavily doped second layer, thinner than said first layer, of the same semiconductor material and of a second conductivity type; c. localized diffusion in selected areas of the impurities present in the said second layer into the said first layer by causing patterned light of appreciable intensity to fall on the surface of the said second layer; d. uniform removal by ion milling of the said second layer, thus removing from nonselected areas essentially all of the impurities associated with the said second layer of a second conductivity type, while leaving these said impurities distributed through the thickness of the said first layer in the said selected areas; and, e. thermal annealing of the grown crystal-layer increment by using unpatterned (uniform) incident light.
Claim 32
Dependent Claim
67 words
Method of claim 28 wherein said integrated circuit comprises at least one material from the following group: a. silicon; b. germanium; c. diamond; d. silicon carbide; e. aluminum antimonide; f. boron phosphide; g. gallium arsenide; h. gallium aluminum arsenide; i. gallium phosphide; j. indium phosphide; k. cadmium sulfide; l. cadmium selenide; m. cadmium telluride; n. zinc oxide; o. zinc sulfide; p. monocrystalline insulator; and, q. monocrystalline metal.
Claim 33
Dependent Claim
22 words
Method of claim 28 carried out in a way that subjects the work in process to relatively small temperature and pressure excursions.
Claim 34
Dependent Claim
10 words
Method of claim 28 carried out in a closed system.
Claim 35
Dependent Claim
10 words
Method of claim 28 carried through in a single-pumpdown operation.
Claim 36
Dependent Claim
7 words
Method of claim 28 comprising in-situ patterning.
Claim 37
Dependent Claim
18 words
Method of claim 28 comprising patterning by means of a liquid-crystal display that serves as a pattern generator.
Claim 38
Dependent Claim
19 words
Method of claim 28 during which the crystal-growth surface remains substantially plane from start to finish of said procedure.
Claim 39
Dependent Claim
10 words
Method of claim 28 carried out in a single system.
Claim 40
Dependent Claim
10 words
Method of claim 28 carried out in a quasicontinuous manner.
Claim 41
Dependent Claim
199 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern created by a procedure that comprises at least four of the following five steps: a. growth by sputter epitaxy of a lightly doped first layer of semiconductor material of a first conductivity type; b. growth by sputter epitaxy of a heavily doped second layer, thinner than said first layer, of the same semiconductor material and of a second conductivity type; c. localized diffusion in selected areas of the impurities present in the said second layer into the said first layer by causing patterned light of appreciable intensity to fall on the surface of the said second layer; d. uniform removal by ion milling of the said second layer, thus removing from nonselected areas essentially all of the impurities associated with the said second layer of a second conductivity type, while leaving these said impurities distributed through the thickness of the said first layer in the said selected areas; and, e. thermal annealing of the grown crystal-layer increment by using unpatterned (uniform) incident light.
Claim 42
Dependent Claim
199 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern created by a procedure that comprises at least four of the following five steps: a. growth by sputter epitaxy of a lightly doped first layer of semiconductor material of a first conductivity type; b. growth by sputter epitaxy of a heavily doped second layer, thinner than said first layer, of the same semiconductor material and of a second conductivity type; c. localized diffusion in selected areas of the impurities present in the said second layer into the said first layer by causing patterned light of appreciable intensity to fall on the surface of the said second layer; d. uniform removal by ion milling of the said second layer, thus removing from nonselected areas essentially all of the impurities associated with the said second layer of a second conductivity type, while leaving these said impurities distributed through the thickness of the said first layer in the said selected areas; and, e. thermal annealing of the grown crystal-layer increment by using unpatterned (uniform) incident light.
Claim 43
Dependent Claim
195 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern created by a procedure that comprises the following five steps: a. growth by sputter epitaxy of a lightly doped first layer of semiconductor material of a first conductivity type; b. growth by sputter epitaxy of a heavily doped second layer, thinner than said first layer, of the same semiconductor material and of a second conductivity type; c. localized diffusion in selected areas of the impurities present in the said second layer into the said first layer by causing patterned light of appreciable intensity to fall on the surface of the said second layer; d. uniform removal by ion milling of the said second layer, thus removing from nonselected areas essentially all of the impurities associated with the said second layer of a second conductivity type, while leaving these said impurities distributed through the thickness of the said first layer in the said selected areas; and, e. thermal annealing of the grown crystal-layer increment by using unpatterned (uniform) incident light.
Claim 44
Dependent Claim
195 words
Method for fabricating a three-dimensional integrated circuit that is substantially monocrystalline and that comprises a three-dimensional doping pattern achieved by the growth of a sequence of discrete crystal-layer increments, each increment having a two-dimensional doping pattern created by a procedure that comprises the following five steps: a. growth by sputter epitaxy of a lightly doped first layer of semiconductor material of a first conductivity type; b. growth by sputter epitaxy of a heavily doped second layer, thinner than said first layer, of the same semiconductor material and of a second conductivity type; c. localized diffusion in selected areas of the impurities present in the said second layer into the said first layer by causing patterned light of appreciable intensity to fall on the surface of the said second layer; d. uniform removal by ion milling of the said second layer, thus removing from nonselected areas essentially all of the impurities associated with the said second layer of a second conductivity type, while leaving these said impurities distributed through the thickness of the said first layer in the said selected areas; and, e. thermal annealing of the grown crystal-layer increment by using unpatterned (uniform) incident light.
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