US5878060A
Expired / Lapsed
US
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Viterbi decoding apparatus and viterbe decoding method
Assignee: Sony Corp
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Filing: 1997-03-24
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Granted: 1999-03-02
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Expires: 2017-03-24
Abstract
Abstract Survivor sequences information is supplied to a RAM 61-1 and a RAM 61-2 as an input Din. The RAM 61-1 and the RAM 61-2 perform an interleaving operation and store the survivor sequences information alternately in accordance with a clock CK1 and a clock CK2 differing in phase from the clock CK1 by half a period. The phases of the clock CK1 and the phase of the clock CK2 are delayed by half a period when a write operation is switched to a read operation with data being outputted at a selector 62 in an appropriate order accordingly. Traced-back data is then inputted from terminal A and terminal B to the selector 62 and outputted from a terminal X after one of these items of data has been selected at a prescribed timing.
Inventors
- 👤 Masataka Wakamatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:32
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/27; H03M13/2703; H03M13/37; H03M13/39; H03M13/3961; H03M13/41; H03M13/4107; H03M13/4161
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
144 words
A Viterbi decoding apparatus for generating maximum likelihood decoded data as a result of analyzing survivor sequences information stored in a memory unit by carrying out traceback, said Viterbi decoding apparatus comprising: clock generating means for generating a first clock and a second clock and for delaying said first and second clocks by half a period when traceback is started, said second clock having a phase inverse of that of said first clock; first memory means for memorizing half of said survivor sequences information in accordance with said first clock; second memory means for memorizing half of said survivor sequences information in accordance with said second clock; and reading out means for reading out said survivor sequences information memorized in said first memory means and said second memory means in a prescribed order in accordance with said first clock and said second clock, respectively.
Claim 2
Dependent Claim
144 words
A Viterbi decoding apparatus for generating maximum likelihood decoded data as a result of analyzing survivor sequences information stored in a memory unit by carrying out traceback, said Viterbi decoding apparatus comprising: clock generating means for generating a first clock and a second clock and for delaying said first and second clocks by half a period when traceback is started, said second clock having a phase inverse of that of said first clock; first memory means for memorizing half of said survivor sequences information in accordance with said first clock; second memory means for memorizing half of said survivor sequences information in accordance with said second clock; and reading out means for reading out said survivor sequences information memorized in said first memory means and said second memory means in a prescribed order in accordance with said first clock and said second clock, respectively.
Claim 3
Dependent Claim
42 words
A Viterbi decoding apparatus according to claim 1, wherein said first memory means and said second memory means carry out memorizing and reading out said survivor sequences information in the same address in accordance with said first clock and said second clock.
Claim 4
Dependent Claim
44 words
A Viterbi decoding apparatus according to claim 1 further comprising: selecting means for selecting one of said survivor sequences information inputted from said first memory means and said second memory means so as to output selected one in accordance with a switching control signal.
Claim 5
Dependent Claim
28 words
A Viterbi decoding apparatus according to claim 3, wherein said switching control signal, said first clock and said second clock are signals in synchronism with a master clock.
Claim 6
Dependent Claim
30 words
A Viterbi decoding apparatus according to claim 1, wherein said first memory means and said second memory means are composed of memories and divided into prescribed number of memory banks.
Claim 7
Dependent Claim
78 words
A Viterbi decoding apparatus according to claim 1, wherein said clock generating means comprises: mask signal generating means for generating a mask signal in accordance with a starting signal indicating a start of traceback and said master clock; and frequency dividing means for dividing the frequency of said master clock inputted together with said mask signal in half and delaying said first clock and said second clock by half a period thereof in accordance with said mask signal.
Claim 8
Dependent Claim
135 words
A Viterbi decoding apparatus according to claim 1 further comprising: branch metrics calculating means for carrying out calculation of branch metrics for two paths to state to which transitions are possible from a state, said calculation being carried out for all of states being determined by constraint lengths; and Add Compare Select means for carrying out with respect to each of said two paths addition of said branch metric outputted from said branch metrics calculating means and a path metric of a state from which a transition has been made, and for carrying out selection of a smaller metric presented as a smaller one of the results of said addition, said Add Compare Select means making the result of said selection be memorized in one of said first memory means and said second memory means.
Claim 9
Independent Claim
139 words
A method of carrying out Viterbi decoding for generating maximum likelihood decoded data as a result of analyzing survivor sequences information stored in a memory unit by carrying out traceback, said method comprising the steps of: generating a first clock and a second clock, said first and second clocks being delayed by half a period when traceback is started, said second clock having a phase inverse of that of said first clock; memorizing half of said survivor sequences information in first memory means in accordance with said first clock; memorizing half of said survivor sequences information in second memory means in accordance with said second clock; and reading out said survivor sequences information memorized in said first memory means and said second memory means in a prescribed order in accordance with said first clock and said second clock, respectively.
Claim 10
Independent Claim
139 words
A method of carrying out Viterbi decoding for generating maximum likelihood decoded data as a result of analyzing survivor sequences information stored in a memory unit by carrying out traceback, said method comprising the steps of: generating a first clock and a second clock, said first and second clocks being delayed by half a period when traceback is started, said second clock having a phase inverse of that of said first clock; memorizing half of said survivor sequences information in first memory means in accordance with said first clock; memorizing half of said survivor sequences information in second memory means in accordance with said second clock; and reading out said survivor sequences information memorized in said first memory means and said second memory means in a prescribed order in accordance with said first clock and said second clock, respectively.
Claim 11
Dependent Claim
50 words
A method of carrying out Viterbi decoding according to claim 8, wherein said steps of memorizing and reading out said survivor sequences information in said first memory means and said second memory means are carried out in the same address in accordance with said first clock and said second clock.
Claim 12
Dependent Claim
38 words
A method of carrying out Viterbi decoding according to claim 8 further comprising the steps of: selecting one of said survivor sequences information read out from said first memory means and said second memory means for being outputted.
Claim 13
Dependent Claim
122 words
A method of carrying out Viterbi decoding according to claim 8 further comprising the steps of: carrying out calculation of branch metric for two paths to states to which transitions are possible from a state, said calculation being carried out for all of states being determined by constraint lengths; carrying out with respect to each of said two paths addition of said branch metric outputted from said branch metrics calculating means and a path metric of a state from which a transition has been made; carrying out selection of a smaller metric presented as a smaller one of the results of said addition; and memorizing the result of said selection in one of said first memory means and said second memory means.
References Cited (Backward Citations)
US5430768A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-03-01 | 2002-08-31 | 2003-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-01 | 2006-08-31 | 2007-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-01 | 2010-08-31 | 2011-03-02 | $7700.00 | Window Closed / Lapsed |