US5551044A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for interrupt/SMI# ordering
Assignee: Intel Corp
•
Filing: 1994-12-01
•
Granted: 1996-08-27
•
Expires: 2014-12-01
Abstract
Abstract A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.
Inventors
- 👤 Nilesh V. Shah
- 👤 Jeffrey L. Rabe
- 👤 Zohar Bogin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
120 words
A circuit for controlling interrupt request signal transmission in a computer system comprising: an input for receiving an interrupt request signal from an external component; first circuitry coupled to said input for generating a system management interrupt (SMI) signal in response to said interrupt request signal from said external component wherein said SMI signal causes a processor to switch to a fully operational mode; second circuitry coupled to said input for generating an interrupt request signal to said processor in response to said interrupt request signal from said external component; and a signal processing circuit coupled to said second circuitry for suppressing transmission of said interrupt request signal to said processor until said SMI signal is transmitted to said processor.
Claim 2
Dependent Claim
120 words
A circuit for controlling interrupt request signal transmission in a computer system comprising: an input for receiving an interrupt request signal from an external component; first circuitry coupled to said input for generating a system management interrupt (SMI) signal in response to said interrupt request signal from said external component wherein said SMI signal causes a processor to switch to a fully operational mode; second circuitry coupled to said input for generating an interrupt request signal to said processor in response to said interrupt request signal from said external component; and a signal processing circuit coupled to said second circuitry for suppressing transmission of said interrupt request signal to said processor until said SMI signal is transmitted to said processor.
Claim 3
Dependent Claim
68 words
The circuit of claim 1 wherein said signal processing circuit comprises a gate bit, wherein said second circuitry suppresses transmission of said interrupt request signal to said processor when said gate bit has a first value and wherein said second circuitry generates said interrupt request signal to said processor in response to said interrupt request signal from said external component when said gate bit has a second value.
Claim 4
Dependent Claim
23 words
The circuit of claim 2 wherein said gate bit is coupled to said processor and can be set and cleared by said processor.
Claim 5
Dependent Claim
45 words
The circuit of claim 2 wherein said first circuitry generates said SMI signal in response to said interrupt request signal when said gate bit has a first value and wherein said first circuitry suppresses said SMI signal when said gate bit has a second value.
Claim 6
Dependent Claim
19 words
The circuit of claim 1 wherein said SMI signal causes said processor to switch to a low power mode.
Claim 7
Dependent Claim
13 words
The circuit of claim 1 wherein said circuit resides in an interrupt controller.
Claim 8
Dependent Claim
30 words
The circuit of claim 1 wherein said first circuitry comprises an enable bit for enabling said first circuitry to generate said SMI signal in response to said interrupt request signal.
Claim 9
Dependent Claim
49 words
The circuit of claim 1 wherein said first circuitry receives a plurality of interrupt request signals from a plurality of external components and wherein said first circuitry comprises a plurality of enable bits for selecting interrupt request signals from external components which cause said SMI signal to be generated.
Claim 10
Independent Claim
108 words
A method for controlling interrupt signal transmission in a computer system comprising the steps of: setting an enable bit for an interrupt request signal; receiving an interrupt request signal from an external component; transmitting a system management interrupt (SMI) signal to a processor causing said processor to switch to a fully operational mode; suppressing an interrupt request signal to said processor; and transmitting an interrupt request signal to said processor after transmitting said SMI signal causing said processor to switch to a fully operational mode; transmitting said SMI signal when said processor is in a fully operational mode, causing said processor to switch to a low power mode.
Claim 11
Independent Claim
108 words
A method for controlling interrupt signal transmission in a computer system comprising the steps of: setting an enable bit for an interrupt request signal; receiving an interrupt request signal from an external component; transmitting a system management interrupt (SMI) signal to a processor causing said processor to switch to a fully operational mode; suppressing an interrupt request signal to said processor; and transmitting an interrupt request signal to said processor after transmitting said SMI signal causing said processor to switch to a fully operational mode; transmitting said SMI signal when said processor is in a fully operational mode, causing said processor to switch to a low power mode.
Claim 12
Dependent Claim
29 words
The method of claim 9 further comprising the steps of: setting a gate bit before transmitting said SMI signal; and clearing said gate bit after transmitting said SMI signal.
Claim 13
Dependent Claim
20 words
The method of claim 9 further comprising the step of selecting events which cause said SMI signal to be transmitted.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |