Patent US2327120A successfully refreshed from Google Patents.
US5511200A
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US
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Method and apparatus for providing an enhanced programmable priority interrupt controller
Assignee: Intel Corp
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Filing: 1993-12-01
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Granted: 1996-04-23
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Expires: 2013-12-01
Abstract
Abstract An improved APIC controller which utilizes an improved addressing mechanism for interrupts which provides an additional bit position for priority values so that thirty-two levels of priority may be furnished at sequential addresses within an interrupt vector table in memory. In one embodiment, circuitry is furnished which allows the alternative implementation of either a prior art addressing mechanism or the improved addressing mechanism.
Inventors
- 👤 Muthurajan Jayakumar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
111 words
An improved advanced programmable interrupt controller (APIC controller) comprising: an input/output unit comprising a redirection table with a plurality of registers for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority, communications circuitry, coupled to said input/output unit, to transfer a message containing said interrupt vector, logic circuitry, coupled to said communications circuitry, to determine if a message being transferred containing an interrupt vector is directed to said APIC controller, and prioritization circuitry, coupled to said logic circuitry, to prioritize said interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector.
Claim 2
Dependent Claim
111 words
An improved advanced programmable interrupt controller (APIC controller) comprising: an input/output unit comprising a redirection table with a plurality of registers for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority, communications circuitry, coupled to said input/output unit, to transfer a message containing said interrupt vector, logic circuitry, coupled to said communications circuitry, to determine if a message being transferred containing an interrupt vector is directed to said APIC controller, and prioritization circuitry, coupled to said logic circuitry, to prioritize said interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector.
Claim 3
Dependent Claim
74 words
An improved APIC controller as claimed in claim 1 in which: said APIC controller is coupled to a processor, and is operable to provide said interrupt vectors to said processor in said priority order; and said prioritization circuitry comprises a comparator for comparing five least significant bits of any interrupt vector in a message received by an APIC controller with five least significant bits of any interrupt vector presently being handled by said processor.
Claim 4
Dependent Claim
20 words
An improved APIC controller as claimed in claim 2 wherein said processor handles said interrupt vectors in said priority order.
Claim 5
Dependent Claim
50 words
An improved APIC controller as claimed in claim 3 in which said processor comprises a comparator for comparing five least significant bits of any interrupt vector in a message received by said APIC controller with the least five significant bits of any interrupt vector presently being executed by said processor.
Claim 6
Dependent Claim
87 words
An improved APIC controller as claimed in claim 1 in which said prioritization circuitry comprises: a first multiplexor connected to receive said interrupt vectors in said received message by said APIC controller, a second multiplexor connected to receive interrupt vectors presently being handled under control of said APIC controller, and control circuitry for causing the first and second multiplexors to transfer the four most significant bits of said interrupt vectors furnished to the first and second multiplexors to said comparator instead of the five least significant bits.
Claim 7
Dependent Claim
98 words
An improved advanced programmable interrupt controller (APIC controller) comprising: a plurality of means for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority, means, coupled to said storing meads, for transferring a message containing one of said interrupt vectors, logic means, coupled to said transferring means, for determining if said message being transferred is directed to an APIC controller and means, coupled to said logic means, for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of said interrupt vector.
Claim 8
Dependent Claim
98 words
An improved advanced programmable interrupt controller (APIC controller) comprising: a plurality of means for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority, means, coupled to said storing meads, for transferring a message containing one of said interrupt vectors, logic means, coupled to said transferring means, for determining if said message being transferred is directed to an APIC controller and means, coupled to said logic means, for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of said interrupt vector.
Claim 9
Dependent Claim
51 words
An improved APIC controller as claimed in claim 6 in which said execution means comprises comparator means for comparing five least significant bits of any interrupt vector in a message received by said APIC controller with five least significant bits of any interrupt vector presently being executed by said execution means.
Claim 10
Dependent Claim
36 words
An improved APIC controller as claimed in claim 6 further comprising: means for executing interrupt vectors in an order based on a priority level which is encoded in four most significant bits of the interrupt vector.
Claim 11
Dependent Claim
51 words
An improved APIC controller as claimed in claim 8 in which said executing means comprises comparator means for comparing five least significant bits of any interrupt vector in a message received by an APIC controller with five least significant bits of any interrupt vector presently being executed by said execution means.
Claim 12
Dependent Claim
82 words
An improved APIC controller as claimed in claim 9 in which said execution means comprises: first multiplexor means connected to receive interrupt vectors in a message received by said APIC controller, second multiplexor means connected to receive interrupt vectors presently being executed under control of said APIC controller, and means for causing the first and second multiplexors to transfer either four most significant bits or five least significant bits of interrupt vectors furnished to the first and second multiplexors to the comparator.
Claim 13
Dependent Claim
130 words
A computer system comprising: a central processing unit; main memory; a bus for transferring data, addresses, and control signals; and an improved advanced programmable interrupt controller (APIC controller) connected to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising: an input/output unit including a redirection table with a plurality of registers for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority, circuitry for transferring a message containing an interrupt vector, logic circuitry for determining if a message being transferred containing an interrupt vector is directed to said APIC controller, and circuitry for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vectors.
Claim 14
Dependent Claim
130 words
A computer system comprising: a central processing unit; main memory; a bus for transferring data, addresses, and control signals; and an improved advanced programmable interrupt controller (APIC controller) connected to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising: an input/output unit including a redirection table with a plurality of registers for storing eight bit programmable interrupt vectors indicating an address of an interrupt in memory and its priority, circuitry for transferring a message containing an interrupt vector, logic circuitry for determining if a message being transferred containing an interrupt vector is directed to said APIC controller, and circuitry for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vectors.
Claim 15
Dependent Claim
75 words
A computer system as claimed in claim 11 in which the circuitry for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector comprises a comparator for comparing five least significant bits of any interrupt vector in a message received by said APIC controller with five least significant bits of any interrupt vector presently being run under control of said APIC controller.
Claim 16
Dependent Claim
39 words
A computer system as claimed in claim 11 wherein said execution circuitry is further operable to execute interrupt vectors in an order based on a priority level which is encoded in four most significant bits of the interrupt vector.
Claim 17
Dependent Claim
52 words
A computer system as claimed in claim 13 in which said execution circuitry comprises a comparator for comparing five least significant bits of any interrupt vector in a message received by an APIC controller with five least significant bits of any interrupt vector presently being executed under control of said APIC controller.
Claim 18
Dependent Claim
82 words
A computer system as claimed in claim 14 in which said execution circuitry comprises: a first multiplexor connected to receive interrupt vectors in a message received by said APIC controller, a second multiplexor connected to receive interrupt vectors presently being executed under control of said APIC controller, and control circuitry for causing the first and second multiplexors to transfer four most significant bits of interrupt vectors furnished to the first and second multiplexors to the comparator instead of five least significant bits.
Claim 19
Dependent Claim
144 words
A computer system comprising: a central processing unit; main memory; a bus, coupled to the central processing unit and to the main memory, for transferring data, addresses, and control signals; and an improved advanced programmable interrupt controller (APIC controller) coupled to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising: a plurality of means for storing eight bit programmable interrupt vector indicating an address of an interrupt in memory and its priority, means for transferring a message containing an interrupt vector, logic means for determining if a message being transferred containing an interrupt vector is directed to an APIC controller, and means, coupled to the central processing unit and to the logic means, for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector.
Claim 20
Dependent Claim
144 words
A computer system comprising: a central processing unit; main memory; a bus, coupled to the central processing unit and to the main memory, for transferring data, addresses, and control signals; and an improved advanced programmable interrupt controller (APIC controller) coupled to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising: a plurality of means for storing eight bit programmable interrupt vector indicating an address of an interrupt in memory and its priority, means for transferring a message containing an interrupt vector, logic means for determining if a message being transferred containing an interrupt vector is directed to an APIC controller, and means, coupled to the central processing unit and to the logic means, for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector.
Claim 21
Dependent Claim
51 words
A computer system as claimed in claim 16 in which the execution means comprises comparator means for comparing five least significant bits of any interrupt vector in a message received by an APIC controller with five least significant bits of any interrupt vector presently being run by the central processing unit.
Claim 22
Dependent Claim
46 words
A computer system as claimed in claim 16 further comprising: means, coupled to the central processing unit and to the logic means, for executing interrupt vectors in an order based on a priority level which is encoded in four most significant bits of the interrupt vector.
Claim 23
Dependent Claim
75 words
A computer system as claimed in claim 18 in which the means for executing interrupt vectors in an order based on a priority level which is encoded in five least significant bits of the interrupt vector comprises comparator means for comparing five least significant bits of any interrupt vector in a message received by the APIC controller with five least significant bits of any interrupt vector presently being executed under control of the APIC controller.
Claim 24
Dependent Claim
81 words
A computer system as claimed in claim 19 in which the execution means comprises: first multiplexor means connected to receive interrupt vectors in a message received by the APIC controller, second multiplexor means connected to receive interrupt vectors presently being executed under control of the APIC controller, and means for causing the first and second multiplexors to transfer either four most significant bits or five least significant bits of interrupt vectors furnished to the first and second multiplexors to the comparator.
Claim 25
Independent Claim
141 words
A method for processing interrupts in a computer system including a central processing unit; main memory; a bus for transferring data, addresses, and control signals; and an improved advanced programmable interrupt controller (APIC controller) connected to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising the steps of: receiving an interrupt signal at a redirection table of the APIC controller, generating an interrupt vector for the interrupt signal with the five least significant bits designating the priority of the interrupt signal, sending the interrupt vector to the APIC controller, comparing the priority within the received interrupt vector with the priority of any interrupt vector being executed under control of the APIC controller by comparing the five least significant bits of each interrupt vector, and executing the received interrupt vector in accordance with the comparison.
Claim 26
Independent Claim
141 words
A method for processing interrupts in a computer system including a central processing unit; main memory; a bus for transferring data, addresses, and control signals; and an improved advanced programmable interrupt controller (APIC controller) connected to receive signals on the bus and to transfer interrupt signals to the central processing unit comprising the steps of: receiving an interrupt signal at a redirection table of the APIC controller, generating an interrupt vector for the interrupt signal with the five least significant bits designating the priority of the interrupt signal, sending the interrupt vector to the APIC controller, comparing the priority within the received interrupt vector with the priority of any interrupt vector being executed under control of the APIC controller by comparing the five least significant bits of each interrupt vector, and executing the received interrupt vector in accordance with the comparison.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-23 | 1999-10-23 | 2000-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-23 | 2003-10-23 | 2004-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-23 | 2007-10-23 | 2008-04-23 | $7700.00 | Window Closed / Lapsed |