US5367697A
Expired / Lapsed
US
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Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability
Assignee: Bull HN Information Systems Inc
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Filing: 1991-10-22
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Granted: 1994-11-22
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Expires: 2011-10-22
Abstract
Abstract A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.
Inventors
- 👤 George J. Barlow
- 👤 James W. Keeley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1441
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
308 words
A multiprocessor computer system, comprising: first processors having a first kind of interrupt handling means, second processors having a second kind of interrupt handling means, said first and second kind interrupt handling means being different, a system management means for performing system management functions, including detecting pending power shut-downs and sending pending power shut-down messages directed to each of the first processors warning of pending power shut-downs, a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages, the first processors first kind interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors in a known state before power termination, said second processors second kind interrupt handling means not recognizing and responding to said pending power shut-down messages; and a power shut-down means in each of said second processors for responding to said pending power shut-down messagess to control said second kind interrupt handling means to place the second processors in a known state before a power termination, including a bus monitor connected to the system bus and responsive to any pending power shut-down message directed to a first processor for generating an output signal indicating the occurrence of a pending power shut-down message directed to a first processor, non-maskable interrupt logic coupled to the bus monitor and responsive to the generation of said output signal for generating a non-maskable interrupt output signal, the second processor being responsive to the generation of a non-maskable interrupt output signal for querying the non-maskable interrupt logic to determine the nature of the interrupt, and responsive to the detection of a pending power shut-down message directed to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.
Claim 2
Dependent Claim
308 words
A multiprocessor computer system, comprising: first processors having a first kind of interrupt handling means, second processors having a second kind of interrupt handling means, said first and second kind interrupt handling means being different, a system management means for performing system management functions, including detecting pending power shut-downs and sending pending power shut-down messages directed to each of the first processors warning of pending power shut-downs, a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages, the first processors first kind interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors in a known state before power termination, said second processors second kind interrupt handling means not recognizing and responding to said pending power shut-down messages; and a power shut-down means in each of said second processors for responding to said pending power shut-down messagess to control said second kind interrupt handling means to place the second processors in a known state before a power termination, including a bus monitor connected to the system bus and responsive to any pending power shut-down message directed to a first processor for generating an output signal indicating the occurrence of a pending power shut-down message directed to a first processor, non-maskable interrupt logic coupled to the bus monitor and responsive to the generation of said output signal for generating a non-maskable interrupt output signal, the second processor being responsive to the generation of a non-maskable interrupt output signal for querying the non-maskable interrupt logic to determine the nature of the interrupt, and responsive to the detection of a pending power shut-down message directed to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.
Claim 3
Dependent Claim
242 words
A data processing system for providing orderly shut-down of a plurality of data processors operating in said system, said system being of the type wherein said data processors are coupled to a system bus, which bus provides a path for information communication between any two of said processors; comprising: means for transmitting on said bus a message denoting that system power shut-down is imminent; at least one first-type processor, said first-type processor having a first kind of interrupt handling means for monitoring communications transmitted on said bus and responding to said message to initiate execution of a routine for placing said first-type processor into a predetermined state prior to the power shut-down; and at least one second-type processor, said second type processor having a second kind of interrupt handling means different from said first kind of interrupt handling means, said second kind of interrupt handling means not recognizing and responding to said message; apparatus coupled to each of said second type processors comprising: a bus monitor coupled to said bus for monitoring communications transmitted on said bus and responsive to the transmission of said message on said bus for generating an output signal; and a logic unit coupled to said bus monitor and responsive to said output signal for generating an interrupt signal; whereby said second-type processor responds to said interrupt signal to initiate execution of a routine for placing said second-type processor into a predetermined state prior to the power shut-down.
Claim 4
Dependent Claim
242 words
A data processing system for providing orderly shut-down of a plurality of data processors operating in said system, said system being of the type wherein said data processors are coupled to a system bus, which bus provides a path for information communication between any two of said processors; comprising: means for transmitting on said bus a message denoting that system power shut-down is imminent; at least one first-type processor, said first-type processor having a first kind of interrupt handling means for monitoring communications transmitted on said bus and responding to said message to initiate execution of a routine for placing said first-type processor into a predetermined state prior to the power shut-down; and at least one second-type processor, said second type processor having a second kind of interrupt handling means different from said first kind of interrupt handling means, said second kind of interrupt handling means not recognizing and responding to said message; apparatus coupled to each of said second type processors comprising: a bus monitor coupled to said bus for monitoring communications transmitted on said bus and responsive to the transmission of said message on said bus for generating an output signal; and a logic unit coupled to said bus monitor and responsive to said output signal for generating an interrupt signal; whereby said second-type processor responds to said interrupt signal to initiate execution of a routine for placing said second-type processor into a predetermined state prior to the power shut-down.
Claim 5
Dependent Claim
55 words
The system of claim 2, wherein; said second-type processor: queries said logic unit in response to said interrupt signal to determine the kind of event that caused the generation of said interrupt signals; and, initiates execution of said routine when said event is determined to be the detection by said bus monitor of said message.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |