US5353256A
Expired / Lapsed
US
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Block specific status information in a memory device
Assignee: Intel Corp
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Filing: 1993-06-30
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Granted: 1994-10-04
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Expires: 2013-06-30
Abstract
Abstract A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.
Inventors
- 👤 Mickey L. Fandrich
- 👤 Chakravarthy Yarlagadda
- 👤 Rodney R. Rozman
- 👤 Geoffrey A. Gould
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:44
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C16/22; G11C7/00; G11C7/24; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
88 words
A flash memory device, comprising: a plurality of flash array blocks, each flash array block comprising a plurality of flash cells; block status register circuit comprising a plurality of block status registers, each block status register storing a block status for one of the flash array blocks; flash array controller circuit performing program and erase operations on the flash array blocks, the flash array controller maintaining the block status in each block status register; interface circuit enabling read access of the block status registers over a host bus.
Claim 2
Dependent Claim
88 words
A flash memory device, comprising: a plurality of flash array blocks, each flash array block comprising a plurality of flash cells; block status register circuit comprising a plurality of block status registers, each block status register storing a block status for one of the flash array blocks; flash array controller circuit performing program and erase operations on the flash array blocks, the flash array controller maintaining the block status in each block status register; interface circuit enabling read access of the block status registers over a host bus.
Claim 3
Dependent Claim
33 words
The flash memory device of claim 1, wherein for each flash array block the block status comprises a lock bit indicating whether the flash array block is inhibited from program or erase operations.
Claim 4
Dependent Claim
35 words
The flash memory device of claim 1, wherein for each flash array block the block status comprises an op fail bit indicating whether a previous program or erase operation to the flash array block failed.
Claim 5
Dependent Claim
36 words
The flash memory device of claim 1, wherein for each flash array block the block status comprises an abort bit indicating whether a program or erase operation on the flash array block was terminated before completion.
Claim 6
Dependent Claim
38 words
The flash memory device of claim 1, wherein for each flash array block the block status comprises a queue full bit indicating whether a command queue from the interface circuit to the flash array controller circuit is full.
Claim 7
Dependent Claim
40 words
The flash memory device of claim 1, wherein for each flash array block the block status comprises a low Vpp bit indicating whether a low Vpp condition was detected during a program or erase operation on the flash array block.
Claim 8
Dependent Claim
38 words
The flash memory device of claim 1, wherein for each flash array block the block status comprises a ready/busy bit indicating whether the flash array controller is performing a program or erase operation on the flash array block.
Claim 9
Dependent Claim
53 words
The flash memory device of claim 1, wherein the interface circuit generates an override ready/busy bit, and substitutes the override ready/busy bit for the ready/busy bit if a program or erase operation is pending for the flash array block in a command queue from the interface circuit to the flash array controller circuit.
Claim 10
Dependent Claim
140 words
The flash memory device of claim 1, wherein the block status register circuit comprises: array of block status register cells having a plurality of rows and a plurality of columns, each row of the block status register cells storing the block status for one of the flash array blocks; access logic circuit for enabling read and write access of the block status register cells by the flash array controller circuit, and for enabling read access of the block status register cells by the interface circuit, the access logic circuit transferring the block status to each column of the block status register cells, the access logic circuit generating a set of read/write control signals for accessing each row of the block status register cells, the access logic circuit receiving the block status from each column of the block status register cells.
Claim 11
Dependent Claim
48 words
The flash memory device of claim 9, wherein each set of read/write control signals comprises a controller read signal for reads by the flash array controller, a controller write signal for writes by the flash array controller, and an interface read signal for reads by the interface circuit.
Claim 12
Dependent Claim
79 words
The flash memory device of claim 10, wherein each block status register cell comprises: static random access memory (SRAM) cell for storing a bit of the block status under control of the controller write signal; controller read circuit for reading the bit of the block status from the SRAM cell under control of the controller read signal; interface read circuit for reading the bit of the block status from the SRAM cell under control of the interface read signal.
Claim 13
Dependent Claim
76 words
The flash memory device of claim 11, wherein the block status register circuit further comprises a plurality of dummy column cells coupled to receive the interface read signals, the interface read signals causing the dummy column cells to generate a latch control signal, such that the latch control signal is valid after the block status is valid at the access logic circuit, the latch control signal causing the access logic circuit to latch the block status.
Claim 14
Dependent Claim
92 words
A computer system, comprising: flash memory device providing block specific status information for a flash cell array comprising a plurality of flash array blocks, the block specific status information accessible over a host bus; main memory means storing a set of write data for a write operation to the flash cell array; central processing means reading the block specific status information from the flash memory device, the central processing means reading the write data from the main memory means and transferring a write command and the write data over the host bus.
Claim 15
Dependent Claim
92 words
A computer system, comprising: flash memory device providing block specific status information for a flash cell array comprising a plurality of flash array blocks, the block specific status information accessible over a host bus; main memory means storing a set of write data for a write operation to the flash cell array; central processing means reading the block specific status information from the flash memory device, the central processing means reading the write data from the main memory means and transferring a write command and the write data over the host bus.
Claim 16
Dependent Claim
91 words
The computer system of claim 13, wherein the flash memory device comprises: block status register circuit comprising a plurality of block status registers, such that each block status register stores the block status information for one of the flash array blocks; flash array controller circuit receiving the write command over the host bus and performing a program operation on the flash array blocks, the flash array controller maintaining the block status information in each block status register; interface circuit enabling read access of the block status registers over the host bus.
Claim 17
Dependent Claim
36 words
The computer system of claim 14, wherein for each flash array block the block status information comprises a lock bit indicating whether the flash array block is inhibited from the program operation or an erase operation.
Claim 18
Dependent Claim
35 words
The computer system of claim 14, wherein for each flash array block the block status information comprises an op fail bit indicating whether a previous program or erase operation to the flash array block failed.
Claim 19
Dependent Claim
38 words
The computer system of claim 14, wherein for each flash array block the block status information comprises an abort bit indicating whether the program operation or an erase operation on the flash array block was terminated before completion.
Claim 20
Dependent Claim
38 words
The computer system of claim 14, wherein for each flash array block the block status information comprises a queue full bit indicating whether a command queue from the interface circuit to the flash array controller circuit is full.
Claim 21
Dependent Claim
42 words
The computer system of claim 14, wherein for each flash array block the block status information comprises a low Vpp bit indicating whether a low Vpp condition was detected during the program operation or an erase operation on the flash array block.
Claim 22
Dependent Claim
37 words
The computer system of claim 14, wherein for each flash array block the block status information comprises a ready/busy bit indicating whether the program operation or an erase operation is being performed on the flash array block.
Claim 23
Dependent Claim
54 words
The computer system of claim 20, wherein the interface circuit generates an override ready/busy bit, and substitutes the override ready/busy bit for the ready/busy bit if the program operation or an erase operation is pending for the flash array block in a command queue from the interface circuit to the flash array controller circuit.
Claim 24
Dependent Claim
142 words
The computer system of claim 14, wherein the block status register circuit comprises: array of block status register cells having a plurality of rows and a plurality of columns, each row of the block status register cells storing the block status information for one of the flash array blocks; access logic circuit for enabling read and write access of the block status register cells by the flash array controller circuit, and for enabling read access of the block status register cells by the interface circuit, the access logic circuit transferring the block status information to each column of the block status register cells, the access logic circuit generating a set of read/write control signals for accessing each row of the block status register cells, the access logic circuit receiving the block status information from each column of the block status register cells.
Claim 25
Dependent Claim
47 words
The computer system of claim 22, wherein each set of read/write control signals comprises a controller read signal for reads by the flash array controller, a controller write signal for writes by the flash array controller, and an interface read signal for reads by the interface circuit.
Claim 26
Dependent Claim
80 words
The computer system of claim 23, wherein each block status register cell comprises: static random access memory (SRAM) cell for storing a bit of the block status under control of the controller write signal; controller read circuit for reading the bit of the block status information from the SRAM cell under control of the controller read signal; interface read circuit for reading the bit of the block status information from the SRAM cell under control of the interface read signal.
Claim 27
Dependent Claim
77 words
The computer system of claim 24, wherein the block status register circuit further comprises a plurality of dummy column cells coupled to receive the interface read signals, the interface read signals causing the dummy column cells to generate a latch control signal, such that the latch control signal is valid after the block status information is valid at the access logic circuit, the latch control signal causing the access logic circuit to latch the block status information.
Claim 28
Dependent Claim
89 words
A computer system, comprising: circuit for providing block specific status information for a flash cell array comprising a plurality of flash array blocks, such that the block specific status information is accessible over a host bus; main memory means storing a set of write data for a write operation to the flash cell array; central processing means reading the block specific status information, the central processing means reading the write data from the main memory means and transferring a write command and the write data over the host bus.
Claim 29
Dependent Claim
89 words
A computer system, comprising: circuit for providing block specific status information for a flash cell array comprising a plurality of flash array blocks, such that the block specific status information is accessible over a host bus; main memory means storing a set of write data for a write operation to the flash cell array; central processing means reading the block specific status information, the central processing means reading the write data from the main memory means and transferring a write command and the write data over the host bus.
Claim 30
Dependent Claim
146 words
The computer system of claim 26, wherein the circuit for providing block specific status information comprises: circuit for receiving the write command over the host bus, such that the write command specifies the flash array block from among a plurality of available flash array blocks; circuit for storing the write command in a command queue; circuit for retrieving the write command from the command queue and performing the write operation on the flash array block; circuit for accessing a block status register corresponding to the flash array block from among a set of available block status registers, wherein each available block status registers corresponds to one of the available flash array blocks; circuit for setting at least one status bit in the block status register; circuit for reading the block status register and transferring the status bit to the central processing means over the host bus.
Claim 31
Dependent Claim
30 words
The computer system of claim 27, wherein the status bit comprises a lock bit indicating whether the flash array block is inhibited from the write operation or an erase operation.
Claim 32
Dependent Claim
30 words
The computer system of claim 27, wherein the status bit comprises an op fail bit indicating whether a previous write program or erase operation to the flash array block failed.
Claim 33
Dependent Claim
32 words
The computer system of claim 27, wherein the status bit comprises an abort bit indicating whether the write operation or an erase operation on the flash array block was terminated before completion.
Claim 34
Dependent Claim
22 words
The computer system of claim 27, wherein the status bit comprises a queue full bit indicating whether the command queue is full.
Claim 35
Dependent Claim
36 words
The computer system of claim 27, wherein the status bit comprises a low Vpp bit indicating whether a low Vpp condition was detected during the write operation or an erase operation on the flash array block.
Claim 36
Dependent Claim
31 words
The computer system of claim 27, wherein the status bit comprises a ready/busy bit indicating whether the write operation or an erase operation is being performed on the flash array block.
Claim 37
Dependent Claim
53 words
The computer system of claim 27, wherein the circuit for providing block specific status information further comprises circuit for generating an override ready/busy bit, and substituting the override ready/busy bit for the ready/busy bit if the write operation or an erase operation is pending for the flash array block in the command queue.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |