Method and apparatus for integrated circuit diagnosis

Claim 1

An integrated system for simulating and analyzing designs of, and for exercising and probing physical implementations of complex circuits comprising: a schematic editor component of the integrated system for navigating through a design of a circuit, said schematic editor including means for selecting nets of the design, a logic simulator component of the integrated system for providing simulated waveforms at the nets of the design selected in the schematic editor and for providing a set of I/O test vectors, a layout program component of the integrated system providing a net-list level circuit layout of the design; a tester component of the integrated system for applying the test vectors to external nodes of a physical implementation of the design; a probe component of the integrated system for measuring live waveforms at a specific node on the physical implementation of the design; a software layer component of the integrated system, including a user interface and a programmatic interface, linking the schematic editor component to the probe component; means for positioning the probe in response to nets selected on the schematic editor to measure the live waveform at nodes corresponding to the selected nets; an interface component of the integrated system for synchronizing operation of the schematic editor, logic simulator, tester, and probe components; means for displaying in the integrated system the live waveforms and the simulated waveforms corresponding to the selected nets, in real time and side-by side with one another on a single display screen.

Claim 4

A method of diagnosing integrated circuits, comprising: a) selecting one or more nets of interest on a display of a schematic diagram; b) highlighting the selected nets on a display and automatically positioning a probe at a corresponding area on a device under test; c) probing the selected net on the DUT with an e-beam; d) displaying a live waveform for the selected net; e) storing the live waveform; f) simulating a waveform for the selected net; g) displaying the simulated waveform; and h) comparing the simulated and live waveforms; wherein the steps of probing the selected net, displaying the live waveform and storing the live waveform include: providing a set of stimuli to external pins of the DUT, said stimuli corresponding to patterns of stimuli applied when simulating the waveform for the selected net; instructing the probe to sample the live waveform at the corresponding area on the DUT such that the live waveform corresponds in time to the simulated waveform; and retrieving the live waveform from the probe tool and storing it in a memory.

Claim 5

A method of diagnosing integrated circuits, comprising: a) selecting one or more nets of interest on a display of a schematic diagram; b) highlighting the selected nets on a display and automatically positioning a probe at a corresponding area on a device under test; c) probing the selected net on the DUT with an e-beam; d) displaying a live waveform for the selected net; e) storing the live waveform; f) simulating a waveform for the selected net; g) displaying the simulated waveform; and h) comparing the simulated and live waveforms; wherein the steps of probing the selected net, displaying the live waveform and storing the live waveform include: providing a set of stimuli to external pins of the DUT, said stimuli corresponding to patterns of stimuli applied when simulating the waveform for the selected net; instructing the probe to sample the live waveform at the corresponding area on the DUT such that the live waveform corresponds in time to the simulated waveform; and retrieving the live waveform from the probe tool and storing it in a memory.

Claim 6

A method of testing integrated circuits, comprising: (a) providing a schematic design of an integrated circuit on an ECAD system; (b) providing a set of test vectors on the ECAD system for the integrated circuit, said test vectors corresponding to waveforms to be applied to external input nodes of the integrated circuit; (c) providing, on the ECAD system, a set of expected results corresponding to waveforms expected to be observed at external output nodes (pins) of the integrated circuit when exercised according to the test vectors; (d) providing a physical implementation of the integrated circuit as a device under test (DUT); (e) exercising the DUT according to the test vectors; (f) detecting a faulty external output node of the DUT for which output signals resulting from step (e) differ from the expected results; (g) generating a list of internal DUT circuit elements associated with each of the faulty external output node for probing; (h) re-exercising the DUT; (i) probing a circuit element on the DUT from the list of circuit elements while re-exercising the inputs; (j) viewing live waveforms from the element being probed in step (i); (k) viewing simulated waveforms for the element being probed; (l) comparing the simulated waveforms (step (k) and the live waveforms (step (j)); and (m) repeating the steps (h) through (l), element by element, until a faulty element is located.

Claim 7

A method of testing integrated circuits, comprising: (a) providing a schematic design of an integrated circuit on an ECAD system; (b) providing a set of test vectors on the ECAD system for the integrated circuit, said test vectors corresponding to waveforms to be applied to external input nodes of the integrated circuit; (c) providing, on the ECAD system, a set of expected results corresponding to waveforms expected to be observed at external output nodes (pins) of the integrated circuit when exercised according to the test vectors; (d) providing a physical implementation of the integrated circuit as a device under test (DUT); (e) exercising the DUT according to the test vectors; (f) detecting a faulty external output node of the DUT for which output signals resulting from step (e) differ from the expected results; (g) generating a list of internal DUT circuit elements associated with each of the faulty external output node for probing; (h) re-exercising the DUT; (i) probing a circuit element on the DUT from the list of circuit elements while re-exercising the inputs; (j) viewing live waveforms from the element being probed in step (i); (k) viewing simulated waveforms for the element being probed; (l) comparing the simulated waveforms (step (k) and the live waveforms (step (j)); and (m) repeating the steps (h) through (l), element by element, until a faulty element is located.