US5253201A
Expired / Lapsed
US
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Writing control circuit employed in non-volatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-07-24
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Granted: 1993-10-12
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Expires: 2012-07-24
Abstract
Abstract A write control circuit is provided for supplying a gate of an n-channel enhancement-type writing transistor with a voltage corresponding to data when the data is written. The circuit comprises a reference potential-generation circuit, a differential amplifier, and a feedback circuit. The reference potential-generation circuit generates a reference potential substantially equal to the upper limit of that high level of each of the bit lines which is assumed at the time of writing. The differential amplifier has an input terminal to be supplied with the reference potential. A write voltage serving as an operation voltage is applied to the amplifier. The feedback circuit is connected between the other input terminal and output terminal of the differential amplifier. The feedback circuit generates, under the control of the differential amplifier, a write control voltage higher than the reference potential by the threshold voltage of the writing transistor, and applies the write control voltage to the gate of the writing transistor. Also, the feedback circuit feeds a voltage obtained by reducing the write control voltage, back to the other input terminal of the differential amplifier.
Inventors
- 👤 Shigeru Atsumi
- 👤 Hironori Banba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:33
CPC Classifications
G; G11; G11C; G11C16/00; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/26; G05F3/262; G11C16/02; G11C16/06; G11C16/10; G11C16/30; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
318 words
A non-volatile semiconductor memory device comprising: a memory cell array having non-volatile memory cells arranged in rows and columns, each memory cell having a control gate, a floating gate, a source, and a drain; word lines each connected to the control gates of those memory cells of the memory cell array which are arranged in the same row; bit lines being perpendicular to the word lines, and each connected to the drains of those memory cells of the memory cell array which are arranged in the same column; column-selecting transistors each having a current path, which has one end connected to a corresponding one of the bit lines and the other end connected in common to one another; an n-channel enhancement-type writing transistor having a current path, which has an end thereof connected to the other end of each of the column-selecting transistors, and the other end thereof connected to a writing voltage source; and a write control circuit for supplying the gate of the writing transistor with a voltage corresponding to data when the data is written, the write control circuit having reference potential-generation means for generating a reference potential, differential amplifier means to be supplied with a write voltage serving as an operation voltage, from the writing voltage source, the differential amplifier means having an input terminal to be supplied with the reference potential from the reference potential-generation means, and feedback means connected between the other input terminal and output terminal of the differential amplifier means, the feedback means generating, under the control of the differential amplifier means, a write control voltage higher than the reference potential by the threshold voltage of the n-channel enhancement-type writing transistor, and applying the write control voltage to the gate of the n-channel enhancement-type writing transistor, the feedback means feeding a voltage obtained by reducing the write control voltage, back to the other input terminal of the differential amplifier means.
Claim 2
Dependent Claim
318 words
A non-volatile semiconductor memory device comprising: a memory cell array having non-volatile memory cells arranged in rows and columns, each memory cell having a control gate, a floating gate, a source, and a drain; word lines each connected to the control gates of those memory cells of the memory cell array which are arranged in the same row; bit lines being perpendicular to the word lines, and each connected to the drains of those memory cells of the memory cell array which are arranged in the same column; column-selecting transistors each having a current path, which has one end connected to a corresponding one of the bit lines and the other end connected in common to one another; an n-channel enhancement-type writing transistor having a current path, which has an end thereof connected to the other end of each of the column-selecting transistors, and the other end thereof connected to a writing voltage source; and a write control circuit for supplying the gate of the writing transistor with a voltage corresponding to data when the data is written, the write control circuit having reference potential-generation means for generating a reference potential, differential amplifier means to be supplied with a write voltage serving as an operation voltage, from the writing voltage source, the differential amplifier means having an input terminal to be supplied with the reference potential from the reference potential-generation means, and feedback means connected between the other input terminal and output terminal of the differential amplifier means, the feedback means generating, under the control of the differential amplifier means, a write control voltage higher than the reference potential by the threshold voltage of the n-channel enhancement-type writing transistor, and applying the write control voltage to the gate of the n-channel enhancement-type writing transistor, the feedback means feeding a voltage obtained by reducing the write control voltage, back to the other input terminal of the differential amplifier means.
Claim 3
Dependent Claim
48 words
The non-volatile semiconductor memory device according to claim 1, wherein the reference potential-generation means has a plurality of load elements connected in series between the writing voltage source and a ground terminal, the reference potential-generation means outputting the reference potential from a connection node between the load elements.
Claim 4
Dependent Claim
18 words
The non-volatile semiconductor memory device according to claim 2, wherein each of the load elements includes a resistor.
Claim 5
Dependent Claim
23 words
The non-volatile semiconductor memory device according to claim 2, wherein each of the load elements includes a transistor having a diode connection structure.
Claim 6
Dependent Claim
34 words
The non-volatile semiconductor memory device according to claim 4, wherein the transistor is of an enhancement type, and has a source connected to a back gate, and a gate connected to a drain thereof.
Claim 7
Dependent Claim
24 words
The non-volatile semiconductor memory device according to claim 2, wherein the load elements include a resistor and a transistor having a diode connection structure.
Claim 8
Dependent Claim
33 words
The non-volatile semiconductor memory device according to claim 6, wherein the transistor is of an enhancement type, and has a source connected to a back gate, and a gate connected to a drain.
Claim 9
Dependent Claim
75 words
The non-volatile semiconductor memory device according to claim 1, wherein the reference potential generation-means has a constant-current source having an end connected to the writing voltage source, and a first diode having a cathode connected to the other end of the constant-current source, and an anode connected to a ground terminal, the reference potential being output from a connection node between the other end of the constant-current source and the cathode of the first diode.
Claim 10
Dependent Claim
39 words
The non-volatile semiconductor memory device according to claim 8, wherein the constant-current source includes a depletion-type transistor having a drain connected to the writing voltage source, a gate and a source connected to the cathode of the first diode.
Claim 11
Dependent Claim
37 words
The non-volatile semiconductor memory device according to claim 8, further comprising a second diode having an anode connected to the other end of the constant-current source, and a cathode connected to the cathode of the first diode.
Claim 12
Dependent Claim
22 words
The non-volatile semiconductor memory device according to claim 1, wherein the differential amplifier means includes a current-mirror-load type CMOS differential amplifier circuit.
Claim 13
Dependent Claim
136 words
The non-volatile semiconductor memory device according to claim 1, wherein the feedback means is provided with a p-channel enhancement-type transistor having a source connected to the writing voltage source, and a gate to be supplied with an output potential from the differential amplifier means; an n-channel enhancement-type transistor having a gate and a drain connected to the drain of the p-channel enhancement-type transistor; and a first resistor connected between the source of the n-channel enhancement-type transistor and a ground terminal, a junction between the drain of the p-channel enhancement-type transistor and the drain of the n-channel enhancement-type transistor being connected to the gate of the n-channel enhancement-type writing transistor, and a junction between the source of the n-channel enhancement-type transistor and the first resistor being connected to the other input terminal of the differential amplifier means.
Claim 14
Dependent Claim
50 words
The non-volatile semiconductor memory device according to claim 12, further comprising a second resistor connected between the source of the n-channel enhancement-type transistor and the first resistor, and wherein a junction between the first resistor and second resistor is connected to the other input terminal of the differential amplifier means.
Claim 15
Dependent Claim
103 words
The non-volatile semiconductor memory device according to claim 12, further comprising a first n-channel intrinsic-type transistor having a drain and a gate connected to the drain of the p-channel enhancement-type transistor, and a source connected to the drain and gate of the n-channel enhancement-type transistor; and a second n-channel intrinsic-type transistor having a drain connected to the writing voltage source, and a gate connected to a junction between the drain of the p-channel enhancement-type transistor and the drain of the first n-channel intrinsic-type transistor, the source of the second n-channel intrinsic-type transistor being connected to the gate of the n-channel enhancement-type writing transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-11 | 1997-04-12 | 1997-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-11 | 2001-04-12 | 2001-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-11 | 2005-04-12 | 2005-10-12 | $7700.00 | Window Closed / Lapsed |