Method for producing a semiconductor wafer having shallow and deep buried contacts

Claim 2

A semiconductor processing method for producing a semiconductor wafer having shallow buried contacts in a first region of the wafer and deep buried contacts in a second region of the wafer, comprising the steps of: defining first and second active areas of a substrate in respective first and second regions of a semiconductor wafer; initially doping the first active areas of the substrate in the first region with an impurity of a first conductivity type; providing a first conductive layer over the wafer; patterning and etching the first conductive layer to form first conductive runners in the first and second regions; providing a second conductive layer over the wafer; patterning and etching the second conductive layer to form both (a) second conductive runners and (b) conductive etch stop platforms in the second region, the etch stop platforms electrically contacting corresponding second active areas in the second region; providing an insulative layer over the wafer, the insulative layer having an upper surface which is elevationally higher relative to the second active areas in the second region as compared to the first active areas in the first region; patterning and etching the insulative layer to provide (a) first contact openings which extend to the first active areas of the substrate in the first region, and (b) second contact openings which extend to the conductive etch stop platforms provided above the second active areas in the second region; subjecting the wafer to an implant of the first conductivity type impurity after the insulative layer has been patterned and etched to form the first and second openings, the etch stop platforms protecting the second active areas from the implant of the first conductivity type impurity; and providing a third conductive layer over the insulative layer and into the first and second contact openings, the third conductive layer electrically contacting the first active areas in the first region and electrically contacting the etch stop layer in the second region.

Claim 3

A semiconductor processing method according to claim 1 wherein the step of providing a second conductive layer comprises: providing a polysilicon layer over the wafer; providing a silicide layer atop the polysilicon layer; and providing an oxide layer over the silicide layer.

Claim 4

A semiconductor processing method according to claim 1 wherein the step of providing a second conductive layer comprises: providing a polysilicon layer over the wafer; providing a silicide layer atop the polysilicon layer; and providing an oxide layer over the silicide layer; the method further comprising: etching through the insulative layer and the oxide layer using a dry etchant and stopping at one of the silicide layer or the polysilicon layer.

Claim 5

A semiconductor processing method according to claim 1 further comprising doping the second active areas in the second region with an n-type impurity.

Claim 6

A semiconductor processing method according to claim 1 wherein the step of providing a first conductive layer comprises: providing a first polysilicon layer over the wafer; providing a first silicide layer over the polysilicon layer; and providing a first oxide layer over the silicide layer; the step of providing a second conductive layer comprises: providing a second polysilicon layer over the wafer; providing a second silicide layer over the polysilicon layer; and providing a second oxide layer over the silicide layer.

Claim 7

A semiconductor processing method according to claim 1 wherein individual first conductive runners have sides, the method further comprising: forming insulative spacers on the sides of the first conductive runners; patterning and etching the second conductive layer to form conductive etch stop platforms above the second active areas in the second region and extending onto the insulative spacers.

Claim 8

A semiconductor processing method according to claim 1 wherein: the insulative layer is formed of doped oxide; and the step of providing a second conductive layer comprises: providing a polysilicon layer over the wafer; providing a silicide layer over the polysilicon layer; and providing an undoped oxide layer over the silicide layer.

Claim 9

A semiconductor processing method according to claim 7 further comprising etching the doped oxide layer and the undoped oxide layer at approximately the same etch rate.

Claim 10

A semiconductor processing method for producing a semiconductor wafer having shallow buried contacts in a first region of the wafer and deep buried contacts in a second region of the wafer, comprising the steps of: defining first and second active areas of a substrate in respective first and second regions of a semiconductor wafer; initially doping the first active areas of the substrate in the first region with an impurity of a first conductivity type; providing a first conductive layer over the wafer; patterning and etching the first conductive layer to form first conductive runners in the first and second regions; providing a polysilicon layer over the wafer; providing a silicide layer atop the polysilicon layer; providing a first oxide layer over the silicide layer; patterning and etching the first oxide layer, the silicide layer, and the polysilicon layer to form both (a) second conductive runners and (b) conductive etch stop platforms in the second region, the polysilicon layer of the etch stop platforms electrically contacting corresponding second active areas in the second region; providing a second oxide layer over the wafer, the second oxide layer having an upper surface which is elevationally higher relative to the second active areas in the second region as compared to the first active areas in the first region; patterning and etching (a) the second oxide layer to provide first contact openings which extend to the first active areas in the first region, and (b) the first and second oxide layers to provide second contact openings which extend at least to the silicide layer of the etch stop platforms provided above the second active areas in the second region; subjecting the wafer to an implant of the first conductivity type impurity after the insulative layer has been patterned and etched to form the first and second openings, the etch stop platforms protecting the second active areas from the implant of the first conductivity type impurity; and providing a top conductive layer over the second oxide layer and into the first and second contact openings, the top conductive layer electrically contacting the first active areas in the first region and electrically contacting the silicide layer of the etch stop platforms in the second region.

Claim 11

A semiconductor processing method for producing a semiconductor wafer having shallow buried contacts in a first region of the wafer and deep buried contacts in a second region of the wafer, comprising the steps of: defining first and second active areas of a substrate in respective first and second regions of a semiconductor wafer; initially doping the first active areas of the substrate in the first region with an impurity of a first conductivity type; providing a first conductive layer over the wafer; patterning and etching the first conductive layer to form first conductive runners in the first and second regions; providing a polysilicon layer over the wafer; providing a silicide layer atop the polysilicon layer; providing a first oxide layer over the silicide layer; patterning and etching the first oxide layer, the silicide layer, and the polysilicon layer to form both (a) second conductive runners and (b) conductive etch stop platforms in the second region, the polysilicon layer of the etch stop platforms electrically contacting corresponding second active areas in the second region; providing a second oxide layer over the wafer, the second oxide layer having an upper surface which is elevationally higher relative to the second active areas in the second region as compared to the first active areas in the first region; patterning and etching (a) the second oxide layer to provide first contact openings which extend to the first active areas in the first region, and (b) the first and second oxide layers to provide second contact openings which extend at least to the silicide layer of the etch stop platforms provided above the second active areas in the second region; subjecting the wafer to an implant of the first conductivity type impurity after the insulative layer has been patterned and etched to form the first and second openings, the etch stop platforms protecting the second active areas from the implant of the first conductivity type impurity; and providing a top conductive layer over the second oxide layer and into the first and second contact openings, the top conductive layer electrically contacting the first active areas in the first region and electrically contacting the silicide layer of the etch stop platforms in the second region.

Claim 12

A semiconductor processing method according to claim 9 further comprising: initially doping the first active areas in the first regions with a p-type impurity; initially doping the second active areas in the second regions with an n-type impurity; and doping the polysilicon layer with the n-type impurity.

Claim 13

A semiconductor processing method according to claim 10 further comprising out diffusing the n-type impurity from the polysilicon layer into the second active areas.

Claim 14

A semiconductor processing method according to claim 9 further comprising: initially doping the first active areas in the first regions with an n-type impurity; initially doping the second active areas in the second regions with a p-type impurity; and doping the polysilicon layer with the p-type impurity.

Claim 15

A semiconductor processing method according to claim 12 further comprising out diffusing the p-type impurity from the polysilicon layer into the second active areas.

Claim 16

A semiconductor processing method according to claim 9 wherein individual first conductive runners have sides, the method further comprising: forming insulative spacers on the sides of the first conductive runners; patterning and etching the first oxide layer, the silicide layer, and the polysilicon layer to form conductive etch stop platforms above the second active areas in the second region and extending onto the insulative spacers.

Claim 17

A semiconductor processing method according to claim 9 wherein the first oxide layer is undoped and the second oxide layer is doped, further comprising etching the doped second oxide layer and the undoped first oxide layer at approximately the same etch rate.

Claim 18

A semiconductor processing method for producing a semiconductor wafer having shallow buried contacts in a first region of the wafer and deep buried contacts in a second region of the wafer, comprising the steps of: defining first and second active areas of a substrate in respective first and second regions of a semiconductor wafer; providing a first conductive layer over the wafer; patterning and etching the first conductive layer to form first conductive runners in the first and second regions; providing a polysilicon layer over the wafer; providing a silicide layer atop the polysilicon layer; providing an undoped first oxide layer over the silicide layer; patterning and etching the first oxide layer, the silicide layer, and the polysilicon layer to form both (a) second conductive runners and (b) conductive etch stop platforms in the second region, the polysilicon layer of the etch stop platforms electrically contacting corresponding second active areas in the second region; providing a doped second oxide layer over the wafer, the second oxide layer having an upper surface which is elevationally higher relative to the second active areas in the second region as compared to the first active areas in the first region; patterning and etching (a) the doped second oxide layer to provide first contact openings which extend to the first active areas in the first region, and (b) the undoped first oxide layer and the doped second oxide layer to provide second contact openings which extend at least to the silicide layer of the etch stop platforms provided above the second active areas in the second region, the doped second oxide layer and the undoped first oxide layer being etched at approximately the same etch rate; and providing a top conductive layer over the second oxide layer and into the first and second contact openings, the top conductive layer electrically contacting the first active areas in the first region and electrically contacting the silicide layer of the etch stop platforms in the second region.

Claim 19

A semiconductor processing method for producing a semiconductor wafer having shallow buried contacts in a first region of the wafer and deep buried contacts in a second region of the wafer, comprising the steps of: defining first and second active areas of a substrate in respective first and second regions of a semiconductor wafer; providing a first conductive layer over the wafer; patterning and etching the first conductive layer to form first conductive runners in the first and second regions; providing a polysilicon layer over the wafer; providing a silicide layer atop the polysilicon layer; providing an undoped first oxide layer over the silicide layer; patterning and etching the first oxide layer, the silicide layer, and the polysilicon layer to form both (a) second conductive runners and (b) conductive etch stop platforms in the second region, the polysilicon layer of the etch stop platforms electrically contacting corresponding second active areas in the second region; providing a doped second oxide layer over the wafer, the second oxide layer having an upper surface which is elevationally higher relative to the second active areas in the second region as compared to the first active areas in the first region; patterning and etching (a) the doped second oxide layer to provide first contact openings which extend to the first active areas in the first region, and (b) the undoped first oxide layer and the doped second oxide layer to provide second contact openings which extend at least to the silicide layer of the etch stop platforms provided above the second active areas in the second region, the doped second oxide layer and the undoped first oxide layer being etched at approximately the same etch rate; and providing a top conductive layer over the second oxide layer and into the first and second contact openings, the top conductive layer electrically contacting the first active areas in the first region and electrically contacting the silicide layer of the etch stop platforms in the second region.