Baseband modulation system with improved ROM-based digital filter

Claim 2

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce desired I and Q output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined partial sum signal terms can be looked up as functions of address bits applied thereto, the predetermined partial sum signal terms being combinable to form the desired I and Q output signals, each of the predetermined partial sum signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; addressing the memories with the derived address bits corresponding thereto to produce partial sum signal term outputs; and combining the partial sum signal term outputs produced from said memories to yield the desired I and Q output signals.

Claim 3

The method of claim 1 in which the predetermined partial sum signal terms include a sine term and a cosine term.

Claim 4

The method of claim 1 which further comprises converting the desired I and Q output signals into analog form and modulating an RF signal with said analog signals.

Claim 5

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce first and second desired output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined signal terms can be looked up as functions of address bits applied thereto, the predetermined signal terms being combinable to form the first and second desired output signals, each of the predetermined signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; addressing the memories with the derived address bits corresponding thereto to produce signal term outputs; and combining the signal term outputs produced from said memories to yield the first and second desired output signals; said combining step comprising summing the outputs produced from first and second of said memories, and taking the difference between the outputs produced from third and fourth of said memories.

Claim 6

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce first and second desired output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined signal terms can be looked up as functions of address bits applied thereto, the predetermined signal terms being combinable to form the first and second desired output signals, each of the predetermined signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; addressing the memories with the derived address bits corresponding thereto to produce signal term outputs; and combining the signal term outputs produced from said memories to yield the first and second desired output signals; said combining step comprising summing the outputs produced from first and second of said memories, and taking the difference between the outputs produced from third and fourth of said memories.

Claim 7

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce first and second desired output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined signal terms can be looked up as functions of address bits applied thereto, the predetermined signal terms being combinable to form the first and second desired output signals, each of the predetermined signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; addressing the memories with the derived address bits corresponding thereto to produce signal term outputs; and combining the signal term outputs produced from said memories to yield the first and second desired output signals, said combining step including providing outputs produced from said memories to a digital adder.

Claim 8

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce first and second desired output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined signal terms can be looked up as functions of address bits applied thereto, the predetermined signal terms being combinable to form the first and second desired output signals, each of the predetermined signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; addressing the memories with the derived address bits corresponding thereto to produce signal term outputs; and combining the signal term outputs produced from said memories to yield the first and second desired output signals, said combining step including providing outputs produced from said memories to a digital adder.

Claim 9

In a DQPSK modulation technique comprising the steps: providing a series of input data comprised of two-bit symbols; processing the series of input data to yield first and second digital data streams; differentially encoding the first and second digital data streams; buffering the differentially encoded first and second data streams into two words, N 1 and N 2 , each of said words being comprised of N bits; generating a cycling M-bit subinterval count; using the two N-bit words, in conjunction with the cycling M-bit subinterval count, to address look-up table-based filters to thereby produce filtered I and Q output data; an improvement wherein the look-up tables in said filters can be addressed with a number of address bits less than N+N+M, the improvement comprising: defining each of the I and Q outputs in terms of sums and differences of sine terms and cosine terms; providing a first memory that serves as a look-up table for the sine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 1 , the M-bit subinterval counter, and a P-bit modulo counter, where P is less than N; providing a second memory that serves as a look-up table for the cosine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 1 , the M-bit subinterval counter, and the P-bit modulo counter; providing a third memory that serves as a look-up table for the sine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 2 , the M-bit subinterval counter, and the P-bit modulo counter; providing a fourth memory that serves as a look-up table for the cosine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 2 , the M-bit subinterval counter, and the P-bit modulo counter; and summing the outputs from two of said memories and computing the differences between the outputs of two of said memories to yield filtered digital I and Q output signals; wherein the look-up tables are each addressed by just N+M+P bits, instead of N+N+M bits.

Claim 10

In a DQPSK modulation technique comprising the steps: providing a series of input data comprised of two-bit symbols; processing the series of input data to yield first and second digital data streams; differentially encoding the first and second digital data streams; buffering the differentially encoded first and second data streams into two words, N 1 and N 2 , each of said words being comprised of N bits; generating a cycling M-bit subinterval count; using the two N-bit words, in conjunction with the cycling M-bit subinterval count, to address look-up table-based filters to thereby produce filtered I and Q output data; an improvement wherein the look-up tables in said filters can be addressed with a number of address bits less than N+N+M, the improvement comprising: defining each of the I and Q outputs in terms of sums and differences of sine terms and cosine terms; providing a first memory that serves as a look-up table for the sine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 1 , the M-bit subinterval counter, and a P-bit modulo counter, where P is less than N; providing a second memory that serves as a look-up table for the cosine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 1 , the M-bit subinterval counter, and the P-bit modulo counter; providing a third memory that serves as a look-up table for the sine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 2 , the M-bit subinterval counter, and the P-bit modulo counter; providing a fourth memory that serves as a look-up table for the cosine term in response to an input datum applied as an address thereto, the input datum comprising N-bit word N 2 , the M-bit subinterval counter, and the P-bit modulo counter; and summing the outputs from two of said memories and computing the differences between the outputs of two of said memories to yield filtered digital I and Q output signals; wherein the look-up tables are each addressed by just N+M+P bits, instead of N+N+M bits.

Claim 11

In a method of DQPSK modulation in which input data symbols are decomposed into first and second components and filtered to produce first and second components of an output data signal, an improvement comprising: producing the first output data signal by addressing a plurality of look-up table memories with addresses derived from the components of the input data symbols to yield a plurality of partial sums, and summing said partial sums to produce the first output data signal; and producing the second output data signal by addressing a plurality of look-up table memories with addresses derived from the components of the input data symbols to yield a plurality of partial sums, and summing said partial sums to produce the second output data signal.

Claim 12

In a method of DQPSK modulation in which input data symbols are decomposed into first and second components and filtered to produce first and second components of an output data signal, an improvement comprising: producing the first output data signal by addressing a plurality of look-up table memories with addresses derived from the components of the input data symbols to yield a plurality of partial sums, and summing said partial sums to produce the first output data signal; and producing the second output data signal by addressing a plurality of look-up table memories with addresses derived from the components of the input data symbols to yield a plurality of partial sums, and summing said partial sums to produce the second output data signal.

Claim 13

The method of claim 7 in which: producing the first output data comprises addressing a pair of look-up table memories with addresses derived from the components of the input data signal to yield a first pair of memory output signals and summing said first pair of memory output signals to product the first output data signal; and producing the second output data comprises addressing a pair of look-up table memories with addresses derived from the components of the input data signal to yield a second pair of memory output signals and summing said second pair of memory output signals to produce the second output data signal.

Claim 14

The method of claim 8 in which the first and second pairs of look-up tables contain identical data.

Claim 15

The method of claim 8 in which the same pair of look-up table memories is used in producing both the first and second output data.

Claim 16

A DQPSK baseband modulation system comprising: input means for receiving input symbol data; a differential encoder having an input coupled to said input means and having first and second outputs for providing first and second streams of output data bits, respectively; a first plurality of memories having address lines thereof coupled to the first output of the differential encoder; a second plurality of memories having address lines thereof coupled to the second output of the differential encoder; and first and second summing networks having inputs coupled to outputs of the memories, for producing first and second components of an output signal.

Claim 17

A DQPSK baseband modulation system comprising: input means for receiving input symbol data; a differential encoder having an input coupled to said input means and having first and second outputs for providing first and second streams of output data bits, respectively; a first plurality of memories having address lines thereof coupled to the first output of the differential encoder; a second plurality of memories having address lines thereof coupled to the second output of the differential encoder; and first and second summing networks having inputs coupled to outputs of the memories, for producing first and second components of an output signal.

Claim 18

The modulation system of claim 11 in which: the first summing network has a first input coupled to an output of one of the first plurality of memories and a second input coupled to an output of one of the second plurality of memories.

Claim 19

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce first and second desired output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined signal terms can be looked up as functions of address bits applied thereto, the predetermined signal terms being combinable to form the first and second desired output signals, each of the predetermined signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; address the memories with the derived address bits corresponding thereto to produce signal term outputs; and combining the signal term outputs produced from said memories to yield the first and second desired output signals; said predetermined signal terms include a sine term and a cosine term being given by the following equations: ##EQU9##

Claim 20

In a digital filtering methodology wherein N samples of a digital input signal comprised of M-bit symbols are decomposed into first and second input signals and are used in addressing a memory in order to produce first and second desired output signals, said output signals corresponding to the first and second input signals filtered with desired filter characteristics, an improvement comprising the steps: providing a plurality of memories in which predetermined signal terms can be looked up as functions of address bits applied thereto, the predetermined signal terms being combinable to form the first and second desired output signals, each of the predetermined signal terms being a function of less than M*N bits; deriving address bits for each of said memories from the N samples of the digital input signal; address the memories with the derived address bits corresponding thereto to produce signal term outputs; and combining the signal term outputs produced from said memories to yield the first and second desired output signals; said predetermined signal terms include a sine term and a cosine term being given by the following equations: ##EQU9##