Patent US3649608A successfully refreshed from Google Patents.
US5126286A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing edge connected semiconductor die
Assignee: Round Rock Research LLC
•
Filing: 1990-10-05
•
Granted: 1992-06-30
•
Expires: 2010-10-05
Abstract
Abstract Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.
Inventors
- 👤 Randal W. Chance
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:59
CPC Classifications
H; H10; H10W; H10W90/00; H10W20/00; H10W20/40; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/834; H10W72/90; H10W72/931; H10W72/932; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
138 words
Method of forming an integrated circuit device having die bond locations on a perimeter of a die, the method comprising: a) preparing a semiconductor wafer, which includes a semiconductor substrate and a plurality of dice, each die being defined by a perimeter, and having circuitry on a face of the die; b) forming a plurality of depressions in the substrate, the depressions each extending from locations on the faces to said perimeter; c) depositing conductive material in said depressions to form wirebond pads; d) forming a first group of contacts, contacting said wirebond pad to said circuitry within the die; e) passivating the dice by applying a protective dielectric over the dice; and f) separating the dice, thereby exposing edges of said depression, with the conductive material in said depressions forming die bond locations along said exposed edges.
Claim 2
Dependent Claim
138 words
Method of forming an integrated circuit device having die bond locations on a perimeter of a die, the method comprising: a) preparing a semiconductor wafer, which includes a semiconductor substrate and a plurality of dice, each die being defined by a perimeter, and having circuitry on a face of the die; b) forming a plurality of depressions in the substrate, the depressions each extending from locations on the faces to said perimeter; c) depositing conductive material in said depressions to form wirebond pads; d) forming a first group of contacts, contacting said wirebond pad to said circuitry within the die; e) passivating the dice by applying a protective dielectric over the dice; and f) separating the dice, thereby exposing edges of said depression, with the conductive material in said depressions forming die bond locations along said exposed edges.
Claim 3
Dependent Claim
39 words
Method of forming an integrated circuit as described in claim 1, further comprising: said depressions being formed to extend into the wafer more than 1/500 the thickness of the substrate, but less than 1/5 the thickness of the substrate.
Claim 4
Dependent Claim
39 words
Method of forming an integrated circuit as described in claim 1, further comprising: said depressions being formed to extend into the wafer more than 1/100 the thickness of the substrate, but less than 1/10 the thickness of the substrate.
Claim 5
Dependent Claim
40 words
Method of forming an integrated circuit as described in claim 1, further comprising: isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate prior to depositing conductive material in said depressions.
Claim 6
Dependent Claim
55 words
Method of forming an integrated circuit as described in claim 1, further comprising: isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate, said isolation of said conductive material including forming an oxide layer in the depressions prior to depositing the conductive material in said depressions.
Claim 7
Dependent Claim
57 words
Method of forming an integrated circuit as described in claim 1, further comprising: isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate prior to depositing the conductive material in said depressions, said isolation of said conductive material including providing a layer of doped material in the depressions.
Claim 8
Dependent Claim
57 words
Method of forming an integrated circuit as described in claim 1, further comprising: isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate prior to depositing the conductive material in said depressions, said isolation of said conductive material including providing a layer of doped polysilicon in the depressions.
Claim 9
Dependent Claim
82 words
Method of forming an integrated circuit as described in claim 1, further comprising: a) providing a layer of polysilicon material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate; b) isolating the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate, said isolation including forming an oxide layer in the depressions subsequent to providing said layer of polysilicon, and prior to depositing the conductive material in said depressions.
Claim 10
Dependent Claim
80 words
Method of forming an integrated circuit as described in claim 8, further comprising: a) establishing logic circuit on the wafer in a plurality of fabrication steps, including a plurality of mask steps; b) forming of the plurality of depressions being performed prior to completion of establishing the logic circuitry on the wafer; and c) establishing said isolation of the conductive material in said depressions forming die bond locations along said exposed edges from the semiconductor substrate during said fabrication steps.
Claim 11
Dependent Claim
43 words
Method of forming integrated circuit electronic components, characterized by: a) forming circuitry on a semiconductor wafer, said circuitry including die bond locations; b) forming a passivation layer over said circuitry; and c) exposing the die bond locations by use of a wafer saw.
Claim 12
Dependent Claim
43 words
Method of forming integrated circuit electronic components, characterized by: a) forming circuitry on a semiconductor wafer, said circuitry including die bond locations; b) forming a passivation layer over said circuitry; and c) exposing the die bond locations by use of a wafer saw.
Claim 13
Dependent Claim
46 words
Method of forming integrated circuit components as described in claim 10, further comprising: a) depositing conductive material into a plurality of depressions at the die bond locations; and b) isolating the die bond locations from the semiconductor wafer prior to depositing conductive material in said depressions.
Claim 14
Dependent Claim
36 words
Method of forming integrated circuit components as described in claim 11, further comprising: said isolated of said conductive material including forming an oxide layer in the depression prior to depositing the conductive material in said depressions.
Claim 15
Dependent Claim
29 words
Method of forming integrated circuit components as described in claim 11, further comprising: said isolation of said conductive material including providing a layer of doped material in the depressions.
Claim 16
Dependent Claim
29 words
Method of forming integrated circuit components as described in claim 11, further comprising: said isolation of said conductive material including providing a layer of doped polysilicon in the depressions.
Claim 17
Dependent Claim
74 words
Method of forming integrated circuit components as described in claim 10, further comprising: a) providing a plurality of depressions at the die bond locations; b) providing a layer of polysilicon material in said depressions; c) isolating the layer of polysilicon material in said depressions, said isolation including forming an oxide layer in the depressions subsequent to providing said layer of polysilicon; and d) depositing conductive material into said depressions at the die bond locations.
Claim 18
Dependent Claim
54 words
Method of forming integrated circuit components as described in claim 10, further comprising: a) establishing logic circuitry on the wafer in a plurality of fabrication steps, including a plurality of mask steps; and b) establishing said isolation of the die bond locations along said exposed edges from the semiconductor wafer during said fabrication steps.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |