CMOS output driver

Claim 2

An output driver (100) comprising in combination: an input line (110) for connection to receive an input signal; an output line (112); pull-down means including a transistor (196) having a gate, drain means connected to said output line, and source means connected to receive a power supply potential; capacitor means (192) connected between said pull-down means transistor drain means and said pull-down means transistor gate; first means (170, 172, 174, and 176) including at least an input connected to said input line and an output connected to said pull-down means transistor gate, said first means being responsive to at least the state of said input signal and operative to develop a signal of inverted state on said pull-down means transistor gate, said first means presenting a finite resistance to said pull-down means transistor gate; feedback means including a transistor (190) having a gate, source means connected to said pull-down means transistor gate, and drain means connected to said output line; and second means (130, 134, 150, and 152) including an input connected to said input line and an output connected to said feedback means transistor gate, said second means being responsive to at least the state of said input signal and operative to develop a signal of similar state on said feedback means transistor gate.

Claim 3

An output driver (100) comprising in combination: an input line (110) for connection to receive an input signal; an output line (112); pull-down means including a transistor (196) having a gate, drain means connected to said output line, and source means connected to receive a first power supply potential; capacitor means (192) connected between said pull-down means transistor drain means and said pull-down means transistor gate; first means (170, 172, 174, and 176) including at least an input connected to said input line and an output connected to said pull-down means transistor gate, said first means being responsive to at least the state of said input signal and operative to develop a signal of inverted state on said pull-down means transistor gate, said first means presenting a finite resistance to said pull-down means transistor gate; feedback means including a transistor (190) having a gate, source means connected to said pull-down means transistor gate, and drain means connected to said output line; and gate means (130, 134, 150, and 152) including a first input connected to said input line, a second input connected to said output line, and an output connected to said feedback means transistor gate, said gate means being responsive to at least the state of said input signal and the state of a signal developed on said output line and operative to develop on said feedback means transistor gate a signal the state of which is high except when both the state of the input signal is low and the state of said output line signal is high.

Claim 4

An output driver (100) comprising in combination: an input line (110) for connection to receive an input signal; an output line (112); pull-down means including a transistor (196) having a gate, drain means connected to said output line, and source means connected to receive a first power supply potential; capacitor means (192) connected between said pull-down means transistor drain means and said pull-down means transistor gate; first means (170, 172, 174, and 176) including at least an input connected to said input line and an output connected to said pull-down means transistor gate, said first means being responsive to at least the state of said input signal and operative to develop a signal of inverted state on said pull-down means transistor gate, said first means presenting a finite resistance to said pull-down means transistor gate; feedback means including a transistor (190) having a gate, source means connected to said pull-down means transistor gate, and drain means connected to said output line; and gate means (130, 134, 150, and 152) including a first input connected to said input line, a second input connected to said output line, and an output connected to said feedback means transistor gate, said gate means being responsive to at least the state of said input signal and the state of a signal developed on said output line and operative to develop on said feedback means transistor gate a signal the state of which is high except when both the state of the input signal is low and the state of said output line signal is high.

Claim 5

An output driver as recited in claim 2 further comprising pull-up means including a transistor (194) having a gate connected to said gate means, drain means connected to receive a second power supply potential, and source means connected to said output line, and wherein said gate means is further responsive to at least the state of said input signal and operative to develop a signal of similar state on said pull-up means transistor gate.

Claim 6

An output driver (100) comprising in combination: a first input line (110); a second input line (114); an output line (112); a first inverter (132) having an input connected to said second input line and an output; pull-down means including a transistor (196) having a gate, drain means connected to said output line, and source means connected to receive a first power supply potential; a first NOR gate (170, 172, 174, and 176) having a first input connected to said first input line, a second input connected to said first inverter output, and an output connected to said pull-down means transistor gate, said first NOR gate including first pull-up means employing a power supply line for connection to receive a second power supply potential, a first transistor (170) having a gate and a channel and a second transistor (172) having a gate and a channel connected in series with at least said first pull-up means first transistor channel between said first pull-up means power supply line and said pull-down means transistor gate, a predetermined one of said first pull-up means first and second transistor gates being connected to said first input line and the other one of said first pull-up means first and second transistor gates being connected to said first inverter output, said first pull-up means presenting a finite resistance to said pull-down means transistor gate; and capacitor means 192 connected between said pull-down means transistor drain means and said pull-down means transistor gate.

Claim 7

An output driver (100) comprising in combination: a first input line (110); a second input line (114); an output line (112); a first inverter (132) having an input connected to said second input line and an output; pull-down means including a transistor (196) having a gate, drain means connected to said output line, and source means connected to receive a first power supply potential; a first NOR gate (170, 172, 174, and 176) having a first input connected to said first input line, a second input connected to said first inverter output, and an output connected to said pull-down means transistor gate, said first NOR gate including first pull-up means employing a power supply line for connection to receive a second power supply potential, a first transistor (170) having a gate and a channel and a second transistor (172) having a gate and a channel connected in series with at least said first pull-up means first transistor channel between said first pull-up means power supply line and said pull-down means transistor gate, a predetermined one of said first pull-up means first and second transistor gates being connected to said first input line and the other one of said first pull-up means first and second transistor gates being connected to said first inverter output, said first pull-up means presenting a finite resistance to said pull-down means transistor gate; and capacitor means 192 connected between said pull-down means transistor drain means and said pull-down means transistor gate.

Claim 8

An output driver as recited in claim 4 further comprising: a second inverter (130) having an input connected to said first input line and an output; a third inverter (134) having an input connected to said first inverter output and an output; a NAND gate (152) having a first input connected to said output line, a second input connected to said second inverter output, a third input connected to said third inverter output, and an output; and feedback means including a transistor (190) having a gate connected to said NAND gate output, source means connected to said pull-down means transistor gate, and drain means connected to said output line.

Claim 9

An output driver as recited in claim 5 further comprising: a second NOR gate (150) having a first input connected to said second inverter output, a second input connected to said first inverter output, and an output; and second pull-out means including a transistor (194) having a gate connected to said second NOR gate output, drain means connected to receive said second power supply potential, and source means connected to said output line.