Buffer circuit used in a semiconductor device operating by different supply potentials and method of operating the same

Claim 2

A buffer circuit apparatus operated by different supply potentials comprising: an input terminal receiving an input signal of a first or second logic level; a first power supply terminal to which a predetermined first or second potential is applied; a second power supply terminal to which a predetermined third potential is applied; an output terminal; first and second switching means coupled in parallel between said first power supply terminal and said output terminal; third and fourth switching means coupled in parallel between said second power supply terminal and said output terminal; and controlling means for controlling said first, second, third and fourth switching means in response to an input signal applied to said input terminal, said controlling means, when said predetermined first potential is applied to said first power supply terminal, rendering either one of said first or second switching means conductive and the remaining said switching means non-conductive in response to the input signal of said first logic level applied to said input terminal, and rendering either one of said third or fourth switching means conductive and the remaining switching means non-conductive in response to the input signal of said second logic level applied to said input terminal, and when said predetermined second potential is applied to said first power supply terminal, rendering said first and second switching means conductive and said third and fourth switching means non-conductive in response to the input signal of said first logic level applied to said input terminal, and rendering said third and fourth switching means conductive and said first and second switching means non-conductive in response to the input signal of said second logic level applied to said input terminal.

Claim 3

A buffer circuit apparatus in accordance with claim 1, wherein each of said first, second, third and fourth switching means comprises a field effect device.

Claim 4

A buffer circuit apparatus in accordance with claim 2, wherein said field effect device comprises an MOS field effect transistor.

Claim 5

A buffer circuit apparatus in accordance with claim 1, wherein, said first logic level is high, said second logic level is low, said predetermined second potential is the predetermined power supply potential, said predetermined first potential is higher than said predetermined power supply potential, said predetermined third potential is the ground potential, each of said first and second switching means comprises a P channel MOS field effect transistor, and each of said third and fourth switching means comprises an N channel MOS field effect transistor.

Claim 6

A buffer circuit apparatus in accordance with claim 1, wherein said controlling means further receives a first voltage sense signal when said predetermined first potential is applied to said first power supply terminal, further receives a second voltage sense signal when said predetermined second potential is applied to said first power supply terminal, renders either one of said first or second switching means conductive and the remaining said switching means non-conductive in response to said first voltage sense signal and said input signal of the first logic level, renders either one of said third or fourth switching means conductive and the remaining said switching means non-conductive in response to said first voltage sense signal and said input signal of the second logic level, renders said first and second switching means conductive and said third and fourth switching means non-conductive in response to said second voltage sense signal and said input signal of the first logic level and renders said third and fourth switching means conductive and said first and second switching means non-conductive in response to said second voltage sense signal and said input signal of the second logic level.

Claim 7

A buffer circuit apparatus in accordance with claim 5, wherein said controlling means further receives a first or second output control signal and renders the first to fourth switching means non-conductive in response to said second output control signal.

Claim 8

A buffer circuit apparatus in accordance with claim 6, said controlling means comprises: p1 a first logic circuit rendering said first switching means conductive in response to said first output control signal and said input signal of the first logic level; a second logic circuit rendering said second switching means conductive in response to said first output control signal, said input signal of the first logic level and said second voltage sense signal; a third logic circuit rendering said third switching means conductive in response to said first output control signal and said input signal of the second logic level; and a fourth logic circuit rendering said fourth switching means conductive in response to said first output control signal, said input signal of the second logic level and said second voltage sense signal.

Claim 9

A buffer circuit apparatus in accordance with claim 7, wherein, said first logic level is high, said second logic level is low, said predetermined second potential is the predetermined power supply potential, said predetermined first potential is higher than said predetermined power supply potential, said predetermined third potential is the ground potential, each of said first and second switching means comprises a P channel MOS field effect transistor, and each of said third and fourth switching means comprises an N channel MOS field effect transistor.

Claim 10

A buffer circuit apparatus in accordance with claim 8, wherein said controlling means comprises: a first logic circuit having a first input terminal receiving said first or second output control signal and a second input terminal receiving said input signal of the first or second logic level and outputting a low level signal in response to said first output control signal and said input signal of the first logic level; a second logic circuit having a first input terminal receiving said first or second output control signal, a second input terminal receiving said input signal of the first or second logic level and a third input terminal receiving an inverted signal of said first or second voltage sense signal and outputting a low level signal in response to said first output control signal, and input signal of the first logic level and the inverted signal of said second voltage sense signal; a third logic circuit having a first input terminal receiving an inverted signal of said first or second output control signal and a second input terminal receiving said input signal of the first or second logic level and outputting a high level signal in response to said inverted signal of the first output control signal and said output signal of the second logic level; and a fourth logic circuit having a first input terminal receiving an inverted signal of said first or second output control signal, a second input terminal receiving said input signal of the first or second logic level and a third input terminal receiving said first or second voltage sense signal and outputting a high level signal in response to the inverted signal of said first output control signal, said input signal of the second logic level and said second voltage sense signal; said first switching means has a gate electrode receiving an output of said first logic circuit; said second switching means has a gate electrode receiving the output of said second logic circuit; said third switching means has a gate electrode receiving the output of said third logic circuit; and said fourth switching means has a gate electrode receiving the output of said fourth logic circuit.

Claim 11

A buffer circuit apparatus in accordance with claim 8, wherein said control means comprises: a first logic circuit having a first input terminal receiving said first or second output control signal and a second input terminal receiving said input signal of the first or second logic level, outputting the inverted signal of said input signal in response to said first output control signal and outputting a high level signal in response to said second output control signal; a second logic circuit having a first input terminal receiving the inverted signal of said first or second voltage sense signal and a second input terminal receiving the output of said first logic circuit, outputting a high level signal in response to said first voltage sense signal and outputting the same signal as that of the output of said first logic circuit in response to the inverted signal of said second voltage sense signal; a third logic circuit having a first input terminal receiving the inverted signal of said first or second output control signal and a second input terminal receiving said input signal of the first or second logic level, outputting the inverted signal of said input signal in response to the inverted signal of said first output control signal and outputting a low level signal in response to the inverted signal of said second output control signal; and a fourth logic circuit having a first input terminal receiving said first or second voltage sense signal and a second input terminal receiving the output of said third logic circuit, outputting a low level signal in response to said first voltage sense signal and outputting the same signal as that of the output of said third logic circuit in response to said second voltage sense signal; said first switching means has a gate electrode receiving the output of said first logic circuit; said second switching means has a gate electrode receiving the output of said second logic circuit; said third switching means has a gate electrode receiving the output of said third logic circuit; and said fourth switching means has a gate electrode receiving the output of said fourth logic circuit.

Claim 12

A buffer circuit used in a non-volatile memory device, to which the predetermined supply potential or high potential is applied, said buffer circuit comprising: an input terminal receiving a high level or low level input signal; a first power supply terminal to which said predetermined supply potential or said predetermined high potential is applied; a second power supply terminal to which the ground potential is applied; an output terminal; first and second P channel MOS field effect devices coupled in parallel between said first power supply terminal and said output terminal; third and fourth N channel MOS field effect devices coupled in parallel between said second power supply terminal and said output terminal; and controlling means responsive to an input signal applied to said input terminal for controlling said first, second, third and fourth field effect devices; said controlling means, when said predetermined high potential is applied to said first power supply terminal, rendering either one of said first or second field effect device conductive and the remaining said field effect device non-conductive in response to said input signal of the high level applied to said input terminal, and either one of said third or fourth field effect device conductive and the remaining said field effect device non-conductive in response to said input signal of the low level applied to said input terminal, and when said predetermined supply potential is applied to said first power supply terminal, rendering said first and second field effect devices conductive and said third and fourth field effect devices non-conductive in response to said input signal of the high level applied to said input terminal, and said third and fourth field effect devices conductive and said first and second field effect devices non-conductive in response to said input signal of the low level applied to said input terminal.

Claim 13

A buffer circuit used in a non-volatile memory device, to which the predetermined supply potential or high potential is applied, said buffer circuit comprising: an input terminal receiving a high level or low level input signal; a first power supply terminal to which said predetermined supply potential or said predetermined high potential is applied; a second power supply terminal to which the ground potential is applied; an output terminal; first and second P channel MOS field effect devices coupled in parallel between said first power supply terminal and said output terminal; third and fourth N channel MOS field effect devices coupled in parallel between said second power supply terminal and said output terminal; and controlling means responsive to an input signal applied to said input terminal for controlling said first, second, third and fourth field effect devices; said controlling means, when said predetermined high potential is applied to said first power supply terminal, rendering either one of said first or second field effect device conductive and the remaining said field effect device non-conductive in response to said input signal of the high level applied to said input terminal, and either one of said third or fourth field effect device conductive and the remaining said field effect device non-conductive in response to said input signal of the low level applied to said input terminal, and when said predetermined supply potential is applied to said first power supply terminal, rendering said first and second field effect devices conductive and said third and fourth field effect devices non-conductive in response to said input signal of the high level applied to said input terminal, and said third and fourth field effect devices conductive and said first and second field effect devices non-conductive in response to said input signal of the low level applied to said input terminal.