US4932036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Spread spectrum squaring loop with invalid phase measurement rejection
Assignee: Litton Marine Systems Inc
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Filing: 1989-03-03
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Granted: 1990-06-05
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Expires: 2009-03-03
Abstract
Abstract A squaring loop for a GPS receiver locks to a carrier that is bi-phase modulated with a PRN acquisition code and a data message. The receive signal is down converted and hard limited and phase measurements are made between the rising edges of a local clock and every edge of the hard limited carrier. Phase measurements made with respect to extraneous or missing transitions resulting from the data bits that would result in phase locking instability are removed by a phase evaluation comparison. Phase measurements that are outside of limits determined in accordance with the noise characteristics of the channel are excluded thereby removing measurements that would cause the instability. The phase measurements outside the limits are resonably attributable to data bit transitions rather than to noise.
Inventors
- 👤 Dhanvant H. Goradia
- 👤 Fred W. Phillips
- 👤 Gregory Schluge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:31
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
181 words
Phase detector apparatus for use in a phase locked loop for phase locking to a receive signal in a noisy environment, said receive signal being bi-phase modulated with data bits, comprising: reference clock oscillator means for providing a reference clock signal with rising and falling edges, means for down converting said receive signal to an I.F. signal, means for hard limiting said I.F. signal to provide a hard limited I.F. signal with rising and falling edges and with extraneous or missing edges caused by said data bits, means responsive to said reference clock signal and said hard limited I.F. signal for obtaining phase measurements between predetermined edges of said reference clock signal and said edges of said hard limited I.F. signal, thereby providing a phase measurement signal, said phase measurement signal providing a phase locking error signal for said phase locked loop, said extraneous or missing edges causing phase locking instability, and phase evaluation means responsive to said phase measurement signal for removing phase measurements therefrom caused by said extraneous or missing edges that would result in said phase locking instability.
Claim 2
Dependent Claim
181 words
Phase detector apparatus for use in a phase locked loop for phase locking to a receive signal in a noisy environment, said receive signal being bi-phase modulated with data bits, comprising: reference clock oscillator means for providing a reference clock signal with rising and falling edges, means for down converting said receive signal to an I.F. signal, means for hard limiting said I.F. signal to provide a hard limited I.F. signal with rising and falling edges and with extraneous or missing edges caused by said data bits, means responsive to said reference clock signal and said hard limited I.F. signal for obtaining phase measurements between predetermined edges of said reference clock signal and said edges of said hard limited I.F. signal, thereby providing a phase measurement signal, said phase measurement signal providing a phase locking error signal for said phase locked loop, said extraneous or missing edges causing phase locking instability, and phase evaluation means responsive to said phase measurement signal for removing phase measurements therefrom caused by said extraneous or missing edges that would result in said phase locking instability.
Claim 3
Dependent Claim
55 words
The apparatus of claim 1 wherein said phase evaluation means includes comparison limit means for establishing upper and lower limits above and below which, respectively, said phase measurements are removed from said phase measurement signal, said removed phase measurements being caused by said extraneous or missing edges that would result in said phase locking instability.
Claim 4
Dependent Claim
54 words
The apparatus of claim 2 wherein said phase evaluation means includes means for storing a previously valid phase measurement signal, said phase evaluation means utilizing said previously valid phase measurement signal instead of a current value of said phase measurement signal when said current value of said phase measurement signal is outside said limits.
Claim 5
Dependent Claim
37 words
The apparatus of claim 2 wherein said phase measurement signal exhibits a mean, and said upper and lower limits span a range of approximately 87% of a phase measurement range from 0° to 360° about said mean.
Claim 6
Dependent Claim
37 words
The apparatus of claim 2 wherein said phase measurement signal exhibits a mean, and said upper and lower limits span a range of approximately 313° of a phase measurement range from 0° to 360° about said mean.
Claim 7
Dependent Claim
29 words
The apparatus of claim 2 wherein said phase measurement signal exhibits a mean, and said upper and lower limits correspond to a standard deviation from said mean of ±2.70.
Claim 8
Dependent Claim
26 words
The apparatus of claim 2 wherein said phase measurement signal exhibits a mean of 127, said upper limit comprises 237, and said lower limit comprises 20.
Claim 9
Dependent Claim
19 words
The apparatus of claim 1 wherein said predetermined edges of said reference clock signal comprises said rising edges thereof.
Claim 10
Dependent Claim
49 words
The apparatus of claim 2 wherein said phase evaluation means includes noise level algorithm means responsive to said phase measurement signal for providing an adaptive adjustment signal in accordance with said noisy environment, and means for adjusting said upper and lower limits in accordance with said adaptive adjustment signal.
Claim 11
Dependent Claim
34 words
The apparatus of claim 9 wherein said noise level algorithm means comprises means for generating a running average of the variance of said phase measurement signal so as to provide said adaptive adjustment signal.
Claim 12
Dependent Claim
167 words
Phase detector apparatus for use in a phase locked loop for phase locking to a receive signal in a noisy environment, said receive signal being bi-phase modulated with data bits, comprising: reference clock oscillator means for providing a reference clock signal with rising and falling edges, means for down converting said receive signal to an I.F. signal having zero crossings, said I.F. signal having extraneous or missing zero crossings caused by said data bits, means responsive to said reference clock signal and said I.F. signal for obtaining phase measurements between predetermined edges of said reference clock signal and said zero crossings of said I.F. signal, thereby providing a phase measurement signal, said phase measurement signal providing a phase locking error signal for said phase locked loop, said extraneous or missing zero crossings causing phase locking instability, and phase evaluation means responsive to said phase measurement signal for removing phase measurements therefrom caused by said extraneous or missing zero crossings that would result in said phase locking instability.
Claim 13
Dependent Claim
167 words
Phase detector apparatus for use in a phase locked loop for phase locking to a receive signal in a noisy environment, said receive signal being bi-phase modulated with data bits, comprising: reference clock oscillator means for providing a reference clock signal with rising and falling edges, means for down converting said receive signal to an I.F. signal having zero crossings, said I.F. signal having extraneous or missing zero crossings caused by said data bits, means responsive to said reference clock signal and said I.F. signal for obtaining phase measurements between predetermined edges of said reference clock signal and said zero crossings of said I.F. signal, thereby providing a phase measurement signal, said phase measurement signal providing a phase locking error signal for said phase locked loop, said extraneous or missing zero crossings causing phase locking instability, and phase evaluation means responsive to said phase measurement signal for removing phase measurements therefrom caused by said extraneous or missing zero crossings that would result in said phase locking instability.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |