US4841476A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Extended floating point operations supporting emulation of source instruction execution
Assignee: International Business Machines Corp
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Filing: 1986-10-06
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Granted: 1989-06-20
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Expires: 2006-10-06
Abstract
Abstract In a system which emulates execution of source CPU instructions and includes a translating unit (translator) for converting source instructions to target instructions and a target CPU instruction unit for processing and issuing translated target instructions, provision is made for accelerating instruction, translation, issue, and execution when certain source floating point arithmetic instructions are emulated for execution. When a source floating point arithmetic instruction is emulated, a token is placed in a wait queue in the translator to prevent the translation of any source instructions and issue of any target instructions until condition and interrupt information is available and validated. In addition, emulation of source RX-type floating point instructions is enhanced by provision of registers in the instruction unit which receive X-field denoted operands, and which thereby permit a target CPU execution unit to perform the emulation by conducting register-to-register operations.
Inventors
- 👤 James A. Mitchell
- 👤 John F. Bechdel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30174; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
226 words
In a system for emulating the execution of source CPU instructions received from a computer external to said system, said system including a memory, a target instruction unit which processes and issues translated target instructions, target functional units for executing target instructions, and an instruction translating unit (translator) for receiving and translating said source instructions to translated target instructions, an improvement for accelerating said translating and issuing, said improvement comprising: signal means in said translator for generating a floating point token signal in response to translation of a source floating point arithmetic instruction; outcome means in said floating point unit for generating completion signals indicative of the outcome of the target floating point arithmetic instruction issued in response to said translation, said completion signals being generated in advance of completing the execution of said issued target floating point arithmetic instruction; a multi-stage wait queue including a wait stage in said translator, said multi-stage wait queue connected to said signal and outcome means for receiving and moving said token signal to said wait stage in response to said translation and for removing said token signal from said wait stage in response to said completion signals; and system means connected to said wait stage, said translator, and said target instruction unit for preventing the translation and issue of instructions until said token is removed from said wait stage.
Claim 2
Dependent Claim
226 words
In a system for emulating the execution of source CPU instructions received from a computer external to said system, said system including a memory, a target instruction unit which processes and issues translated target instructions, target functional units for executing target instructions, and an instruction translating unit (translator) for receiving and translating said source instructions to translated target instructions, an improvement for accelerating said translating and issuing, said improvement comprising: signal means in said translator for generating a floating point token signal in response to translation of a source floating point arithmetic instruction; outcome means in said floating point unit for generating completion signals indicative of the outcome of the target floating point arithmetic instruction issued in response to said translation, said completion signals being generated in advance of completing the execution of said issued target floating point arithmetic instruction; a multi-stage wait queue including a wait stage in said translator, said multi-stage wait queue connected to said signal and outcome means for receiving and moving said token signal to said wait stage in response to said translation and for removing said token signal from said wait stage in response to said completion signals; and system means connected to said wait stage, said translator, and said target instruction unit for preventing the translation and issue of instructions until said token is removed from said wait stage.
Claim 3
Dependent Claim
189 words
The improvement of claim 1 wherein said source floating point arithmetic instruction is an RX-type instruction which includes an X field for indicating a first operand in a memory location, and which indicates a second operand in a register location, and said target instruction is an RR-type instruction which indicates a first operand in a register location and a second operand in a register location, said target instruction being executable against the operands of said RX instruction and further including: a register in said target instruction unit for receiving a floating point operand indicated by the X-field of said source instruction; a data interface means in said floating point unit selectively connectable to said register for buffering said operand to said floating point unit; and multiplexing means in said target instruction unit connected to said register, said memory, and said data interface means for transferring said operand from a location in said memory indicated by said X-field to said register prior to the issue of said target instruction and for connecting said data interface means to said register to transfer said operand concurrently with the issued target RR instruction.
Claim 4
Dependent Claim
228 words
The improvement of claim 1 wherein said source instruction is an extended RX-type instruction which includes an X field for indicating a first operand in a memory location, and which indicates a second operand in a register location, and said target instruction is an RR-type instruction which indicates a first operand in a register location and a second operand in a register location, said target instruction being executable against the operands of said RX instruction and further including: first and second registers in said target instruction unit for receiving respective first and second halves of an extended floating point operand indicated by the X-field of said source instruction; a data interface means in said floating point unit selectively connectable to said first and second registers for sequentially buffering said first and second operand halves to said floating point unit; and multiplexing means in said target instruction unit connected to said first and second registers, said memory and said data interface means for transferring the first and second halves of said operand from a location in said memory indicated by said X-field to said first and second registers, respectively, prior to the issue of said target (RR) instruction and for connecting said data interface means successively to said first and second registers to transfer said first and second operand halves concurrently with the issue of said target RR instruction.
Claim 5
Dependent Claim
179 words
In a method for emulating execution of a source floating point RX-type instruction (source instruction), said method executable by an emulation system including a memory for storing operands, a Fisk-translator for translating said source instruction into an RR-type target floating point instruction (target instruction), a target system instruction unit for issuing said target instruction, and a target system floating point unit for executing said target instruction, an improvement comprising steps of: providing a source instruction in the form of RX-type floating point instruction from an instruction source, said RX-type instruction including an X field for indicating a memory location containing an operand; moving the operand indicated by said X-field of said source instruction to a register located in said instruction unit; assembling and issuing a target instruction to the floating point unit for execution using operands of said source instructions; concurrently with said issuing of said target instruction, transferring said operand from said instruction unit register to said floating point unit; and executing said target instruction by combining said operand with an operand contained in said floating point unit.
Claim 6
Dependent Claim
179 words
In a method for emulating execution of a source floating point RX-type instruction (source instruction), said method executable by an emulation system including a memory for storing operands, a Fisk-translator for translating said source instruction into an RR-type target floating point instruction (target instruction), a target system instruction unit for issuing said target instruction, and a target system floating point unit for executing said target instruction, an improvement comprising steps of: providing a source instruction in the form of RX-type floating point instruction from an instruction source, said RX-type instruction including an X field for indicating a memory location containing an operand; moving the operand indicated by said X-field of said source instruction to a register located in said instruction unit; assembling and issuing a target instruction to the floating point unit for execution using operands of said source instructions; concurrently with said issuing of said target instruction, transferring said operand from said instruction unit register to said floating point unit; and executing said target instruction by combining said operand with an operand contained in said floating point unit.
Claim 7
Dependent Claim
230 words
In a method for emulating execution of an extended source floating point RX-type instruction (source instruction), said method executable in an emulation system including a memory for storing operands, a Fisk-type translator for translating said source instruction into an RR-type target floating point instruction (target instruction) for issuing said target instruction, and a target system floating point unit for executing said target instruction, an improvement, comprising the steps of: providing a source instruction in the form of an RX-type floating point instruction from an instruction source said RX-type instructing including an X field for indicating a memory location containing an operand with a first half and a second half; moving said first half of said operand indicated by the X field of said RX-type instruction into a first register located in said instruction unit; moving said second half of said operand into a second register located in said instruction unit; in response to said source instruction, assembling and issuing a target instruction to the floating point unit for execution using operands of said source instruction; concurrently with the issue of said target instruction, transferring said first operand half from said first register to said floating point unit; transferring said second operand half from said second register to said floating point unit; and executing said target instruction by combining said first operand with a second operand in said floating point unit.
Claim 8
Dependent Claim
230 words
In a method for emulating execution of an extended source floating point RX-type instruction (source instruction), said method executable in an emulation system including a memory for storing operands, a Fisk-type translator for translating said source instruction into an RR-type target floating point instruction (target instruction) for issuing said target instruction, and a target system floating point unit for executing said target instruction, an improvement, comprising the steps of: providing a source instruction in the form of an RX-type floating point instruction from an instruction source said RX-type instructing including an X field for indicating a memory location containing an operand with a first half and a second half; moving said first half of said operand indicated by the X field of said RX-type instruction into a first register located in said instruction unit; moving said second half of said operand into a second register located in said instruction unit; in response to said source instruction, assembling and issuing a target instruction to the floating point unit for execution using operands of said source instruction; concurrently with the issue of said target instruction, transferring said first operand half from said first register to said floating point unit; transferring said second operand half from said second register to said floating point unit; and executing said target instruction by combining said first operand with a second operand in said floating point unit.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |