Nonvolatile semiconductor memory device with readout test circuitry

Claim 2

A nonvolatile semiconductor memory device receiving an external column and row address signal that designate a row and a column, comprising: a memory cell array for storing data, including a plurality of memory cells arranged in rows and columns, each memory cell including a nonvolatile transistor; a plurality of row lines, each connected to those of said memory cells arranged on a corresponding row; a plurality of column lines, each connected to those of said memory cells arranged on a corresponding column; column line select transistors for selecting a one of said plurality of column lines; column address buffer means for outputting internal column address signals of a selected memory cell in response to received external column address signals; column decoding means for selectively biasing said column line select transistors to select said column line of said selected memory cell in response to said internal column address signals; row address buffer means for outputting internal row address signals in response to received external row address signals; row decoding means for selectively biasing a row line in response to said internal row address signals; control means, operative in a first and second mode, for controlling said row address buffer means by setting said internal row address signals in a predetermined state to hold said row lines in a nonselected state, wherein, when said control means is in said first mode, said selected column line is set to a first potential and said internal row address signals are set to said predetermined state in response to said received external row address signals, and wherein, when said control means is in said second mode, said selected column line is set to one of said first potential and a second potential corresponding to data stored in said selected memory cell; and sensing means for detecting the potential of said selected column line and for supplying an output signal to an external terminal in response thereto when said control means is in said first and second modes.

Claim 3

A nonvolatile semiconductor memory device according to claim 1, wherein an external power source supplies an external power signal having a power source voltage to said control means, wherein said control means is in said first mode when a voltage of a predetermined external input signal is at least equal to a predetermined voltage greater than said power source voltage, and wherein said control means is in said second mode when the voltage of said external input signal is smaller than said predetermined voltage.

Claim 4

A nonvolatile semiconductor memory device according to claim 2, wherein said predetermined external input signal is one of said external row address signals.

Claim 5

A nonvolatile semiconductor memory device according to claim 1, wherein said sensing means includes reference potential generating means for generating a reference potential, and wherein said sensing means supplies said output signal in response to a comparison between the potential of said selected column line and said generated reference potential.

Claim 6

A nonvolatile semiconductor memory device receiving external column address signals and external row address signals, comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, each memory cell including a nonvolatile transistor; a plurality of row lines, each connected to those of said memory cells arranged on a corresponding row; a plurality of column lines, each connected to those of said memory cells arranged on a corresponding column; column line select transistors for selecting a one of said plurality of column lines; column address buffer means for outputting internal column address signals in response to received external column address signals; column decoding means for selectively biasing said column line select transistors to select said column line in response to said internal column address signals; row address buffer means for outputting internal row address signals in response to received external row address signals; row decoding means, including a plurality of row decoders, for selectively biasing one of said row lines in response to said internal row address signals; control means, operative in a first mode, for controlling said row decoding means connected to one of said row decoders and for setting the row line corresponding to said row decoder at a predetermined potential, said selected column line consequently being set to a first potential when said control means is in said first mode and said received external row address signals are set to a predetermined state; and sensing means for detecting the potential of said selected column line and for supplying an output signal to an external terminal in response thereto when said control means is in said first mode.

Claim 7

A nonvolatile semiconductor memory device receiving external column address signals and external row address signals, comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, each memory cell including a nonvolatile transistor; a plurality of row lines, each connected to those of said memory cells arranged on a corresponding row; a plurality of column lines, each connected to those of said memory cells arranged on a corresponding column; column line select transistors for selecting a one of said plurality of column lines; column address buffer means for outputting internal column address signals in response to received external column address signals; column decoding means for selectively biasing said column line select transistors to select said column line in response to said internal column address signals; row address buffer means for outputting internal row address signals in response to received external row address signals; row decoding means, including a plurality of row decoders, for selectively biasing one of said row lines in response to said internal row address signals; control means, operative in a first mode, for controlling said row decoding means connected to one of said row decoders and for setting the row line corresponding to said row decoder at a predetermined potential, said selected column line consequently being set to a first potential when said control means is in said first mode and said received external row address signals are set to a predetermined state; and sensing means for detecting the potential of said selected column line and for supplying an output signal to an external terminal in response thereto when said control means is in said first mode.

Claim 8

A nonvolatile semiconductor memory device according to claim 5, wherein an external power source supplies an external power signal having a power source voltage, and wherein said control means is in the first mode when a voltage of a predetermined external input signal is at least equal to a predetermined voltage greater than said power source voltage.

Claim 9

A nonvolatile semiconductor memory device according to claim 6, wherein said predetermined external input signal is one of said external row address signals.

Claim 10

A nonvolatile semiconductor memory device receiving external row and column address signals, comprising: a memory cell array for storing data, including a plurality of memory cells arranged in rows and columns, each memory cell including a nonvolatile transistor; a plurality of row lines, each connected to those of said memory cells arranged on a corresponding row; a dummy row line not connected to said memory cells; a plurality of column lines, each connected to those of said memory cells arranged on a corresponding column; a plurality of dummy memory cells arranged in a column, each dummy memory cell including a nonvolatile transistor and connected to said row lines including said dummy row line; a dummy column line connected to said plurality of dummy memory cells commonly; column line select transistors for selecting a one of said column lines; column address buffer means for outputting internal column address signals of a selected memory cell in response to the received external column address signals; column decoding means for selectively biasing said column line select transistors to select said column line of said selected memory cell in response to said internal column address signals; row address buffer means for outputting internal row address signals in response to the received external row address signals; row decoding means for selectively biasing said row line or dummy row line; control means, operative in a first and a second mode, for controlling said row address buffer means and said row decoding means, wherein, in said first mode, said control means sets said internal row address signals in a predetermined state and sets said row decoder means to select only said dummy row line, said selected column line consequently being set to a first potential and wherein, in said second mode, said control means sets said internal row address signals in the predetermined state in response to said received external row address signals, said selected column line consequently being set to one of said first potential and a second potential corresponding to stored data in said selected memory cell; and sensing means for detecting said potential of said column line selected by said column line select transistors and for supplying an output signal to an external terminal in response thereto when said control means is in said first and second modes.

Claim 11

A nonvolatile semiconductor memory device receiving external row and column address signals, comprising: a memory cell array for storing data, including a plurality of memory cells arranged in rows and columns, each memory cell including a nonvolatile transistor; a plurality of row lines, each connected to those of said memory cells arranged on a corresponding row; a dummy row line not connected to said memory cells; a plurality of column lines, each connected to those of said memory cells arranged on a corresponding column; a plurality of dummy memory cells arranged in a column, each dummy memory cell including a nonvolatile transistor and connected to said row lines including said dummy row line; a dummy column line connected to said plurality of dummy memory cells commonly; column line select transistors for selecting a one of said column lines; column address buffer means for outputting internal column address signals of a selected memory cell in response to the received external column address signals; column decoding means for selectively biasing said column line select transistors to select said column line of said selected memory cell in response to said internal column address signals; row address buffer means for outputting internal row address signals in response to the received external row address signals; row decoding means for selectively biasing said row line or dummy row line; control means, operative in a first and a second mode, for controlling said row address buffer means and said row decoding means, wherein, in said first mode, said control means sets said internal row address signals in a predetermined state and sets said row decoder means to select only said dummy row line, said selected column line consequently being set to a first potential and wherein, in said second mode, said control means sets said internal row address signals in the predetermined state in response to said received external row address signals, said selected column line consequently being set to one of said first potential and a second potential corresponding to stored data in said selected memory cell; and sensing means for detecting said potential of said column line selected by said column line select transistors and for supplying an output signal to an external terminal in response thereto when said control means is in said first and second modes.

Claim 12

A nonvolatile semiconductor memory device according to claim 8, wherein said sensing means compares said potential of said column line selected by said column line select transistors with a potential of said dummy column lines and supplies said output signal in response to the comparison.

Claim 13

A nonvolatile semiconductor memory device according to claim 8, wherein said control means is in the first mode when a voltage of a predetermined external input signal is at least equal to a predetermined voltage greater than a power source voltage supplied from a power source through an external terminal, and wherein said control means is in the second mode when the voltage of said predetermined external input signal is smaller than said predetermined voltage.

Claim 14

A nonvolatile semiconductor memory device according to claim 10, wherein said predetermined external input signal is an external control signal and is supplied to said control means.

Claim 15

A nonvolatile semiconductor memory device according to claim 8, further comprising additional dummy memory cells, including nonvolatile transistors connected to said column lines respectively and to said dummy row line commonly, and programming means for selectively programming data in said additional dummy memory cells.

Claim 16

A nonvolatile semiconductor memory device according to claim 12, wherein said programming means supplies high voltage sufficient for programming said nonvolatile transistors connected to said dummy row line.

Claim 17

A nonvolatile semiconductor memory device according to claim 8, wherein said control means comprises: first and second signal-receiving terminals to which external chip-enable and output-enable signals are supplied respectively; high-voltage detecting means, connected to said first signal-receiving terminal, for outputting interval test signals setting said memory device in a test mode when the voltage of said external chip-enable signal is at least equal to a predetermined voltage greater than a power source voltage supplied from a power source through an external terminal; a chip-enable buffer circuit, connected to said first signal-receiving terminal, for generating an internal chip-enable signal setting said memory device in an active or a standby state in response to said external chip-enable signal, wherein, when the memory device is in the test mode, said external chip-enable signal sets said memory device in the active state; an output-enable buffer circuit connected to said second signal-receiving terminal for generating an internal output-enable signal controlling said sensing means to supply said output signal to said external terminal, wherein said output-enable signal enables said sensing means to supply said output signal to said external terminal; and a row line setting circuit for generating an address controlling signal connected to said row address buffer means for setting said row address signals in said predetermined state.

Claim 18

A nonvolatile semiconductor memory device according to claim 14, wherein said control means is set in said first or second mode in response to said output-enable signal when the memory device is in the test mode.

Claim 19

A nonvolatile semiconductor memory device according to claim 15, , wherein said row decoding means includes a plurality of row decoders each connected to a corresponding row line and one of said row decoders further includes a first potential-setting means for setting the potential of a corresponding row line to a preset potential level in response to said internal test signals when the memory device is set in the test mode.

Claim 20

A nonvolatile semiconductor memory device according to claim 16, wherein said row decoding means includes a dummy row decoder connected to said dummy row line and receiving the same internal row address signals as said row decoder including said first potential-setting means, and wherein said dummy row decoder includes a second potential-setting means for setting the potential of said dummy row line to said preset potential level in response to said internal test signals when the memory device is not in the test mode.