US4748559A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for reducing power consumed by a static microprocessor
Assignee: NXP USA Inc
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Filing: 1979-08-09
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Granted: 1988-05-31
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Expires: 1999-08-09
Abstract
Abstract In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.
Inventors
- 👤 Philip S. Smith
- 👤 Kuppuswamy Raghunathan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3228
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
240 words
In a digital computing system which executes software instructions in synchronization with clock signals generated by a master clock oscillator in an enabled condition thereof, apparatus for reducing the energy consumed by said digital system comprising: first logic means for decoding a predetermined software instruction selected for execution by said digital computing system, and for generating a firts control signal in response thereto; first latching means, coupled to said first logic means, for assuming a first state in response to said first control signal, and for assuming a second state in response to a second control signal; second logic means, coupled to said first latching means and interposed between said master clock oscillator and said digital computing system, for inhibiting passage of said clock signals from said master clock oscillator to said digital computing system in response to said first latching means assuming said first state, said second logic means continuing to inhibit passage of said clock signals for a predetermined length of time after said first latching means assumes said second state; and third logic means, coupled to said first latching means, for disabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said first state, and for enabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said second state, whereby the power required therefor is selectively conserved.
Claim 2
Dependent Claim
240 words
In a digital computing system which executes software instructions in synchronization with clock signals generated by a master clock oscillator in an enabled condition thereof, apparatus for reducing the energy consumed by said digital system comprising: first logic means for decoding a predetermined software instruction selected for execution by said digital computing system, and for generating a firts control signal in response thereto; first latching means, coupled to said first logic means, for assuming a first state in response to said first control signal, and for assuming a second state in response to a second control signal; second logic means, coupled to said first latching means and interposed between said master clock oscillator and said digital computing system, for inhibiting passage of said clock signals from said master clock oscillator to said digital computing system in response to said first latching means assuming said first state, said second logic means continuing to inhibit passage of said clock signals for a predetermined length of time after said first latching means assumes said second state; and third logic means, coupled to said first latching means, for disabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said first state, and for enabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said second state, whereby the power required therefor is selectively conserved.
Claim 3
Dependent Claim
15 words
Apparatus according to claim 1 wherein said second control signal comprises of external reset signal.
Claim 4
Dependent Claim
14 words
Apparatus according to claim 1 wherein said second control signal comprises an interrupt signal.
Claim 5
Dependent Claim
240 words
In a digital computing system which executes software instructions in synchronization with clock signals generated by a master clock oscillator in an enabled condition thereof, apparatus for reducing the energy consumed by said digital system comprising: first logic means for executing a predetermined software instruction selected for execution by said digital computing system, and for generating a first control signal in response thereto; first latching means, coupled to said first logic means, for assuming a first state in response to said first control signal, and for assuming a second state in response to a second control signal; second logic means, coupled to said first latching means and interposed between said master clock oscillator and said digital computing system, for inhibiting passage of said clock signals from said master clock oscillator to said digital computing system in response to said first latching means assuming said first state, said second logic means continuing to inhibit passage of said clock signals for a predetermined length of time after said first latching means assumes said second state; and third logic means, coupled to said first latching means, for disabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said first state, and for enabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said second state, whereby the power required therefor is selectively conserved.
Claim 6
Dependent Claim
240 words
In a digital computing system which executes software instructions in synchronization with clock signals generated by a master clock oscillator in an enabled condition thereof, apparatus for reducing the energy consumed by said digital system comprising: first logic means for executing a predetermined software instruction selected for execution by said digital computing system, and for generating a first control signal in response thereto; first latching means, coupled to said first logic means, for assuming a first state in response to said first control signal, and for assuming a second state in response to a second control signal; second logic means, coupled to said first latching means and interposed between said master clock oscillator and said digital computing system, for inhibiting passage of said clock signals from said master clock oscillator to said digital computing system in response to said first latching means assuming said first state, said second logic means continuing to inhibit passage of said clock signals for a predetermined length of time after said first latching means assumes said second state; and third logic means, coupled to said first latching means, for disabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said first state, and for enabling the generation of said clock signals by said master clock oscillator in response to said first latching means assuming said second state, whereby the power required therefor is selectively conserved.
Claim 7
Dependent Claim
15 words
Apparatus according to claim 4 wherein said second control signal comprises an external reset signal.
Claim 8
Dependent Claim
14 words
Apparatus according to claim 4 wherein said second control signal comprises an interrupt signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |