Atrium-controlled heart pacemaker

Claim 2

An atrial-controlled heart pacemaker operable with a maximum AV delay (AVmax), a minimum AV delay (AVmin) and a smallest synchronous interval (SSI) between two ventricular stimulation pulses comprising: means for sensing an atrial event in said heart; means for sensing a ventricular event in said heart; means for supplying a ventricular pulse to said heart after an AV delay following a sensed atrial event; means for controlling said means for supplying said ventricular pulse for operating said pacemaker in a DDD mode when said sensed atrial event occurs after a point in time SSI-AVmin, operating said pacemaker at a highest synchronous rate corresponding to said SSI when said sensed atrial event occurs between points in time SSI-AVmin and SSI-AVmax, and causing no ventricular stimulation pulse to be supplied when said sensed atrial event occurs before said point in time SSI-AVmax; an AV control unit in said means for controlling, said AV control unit normally generating a signal upon the occurrence of each sensed atrial event for initiating generation of a ventricular pulse; means for inhibiting the transmission of said sensed atrial event to said AV-control unit when said sensed atrial event occurs before said point in time SSI-AVmax; a timer in said means for inhibiting, said timer having an input connected to said means for sensing said ventricular event, said timer assuming a first logic state at an output thereof for a period commencing with the occurrence with said ventricular event and concluding at said point in time SSI-AVmax, and thereafter assuming second logic state; and logic means in said means for inhibiting, said logic means having inputs connected to said means for sensing an atrial event and to said output of said timer, and having an output connected to an input of said AV control unit for preventing through-connection of said sensed atrial event to said input of said AV control unit while said output of said timer is in said first logic state.

Claim 3

An atrial-controlled heart pacemaker operable with a maximum AV delay (AVmax), a minimum AV delay (AVmin) and a smallest synchronous interval (SSI) between two ventricular stimulation pulses comprising; means for sensing an atrial event in said heart; means for sensing a ventricular event in said heart; means for supplying a ventricular pulse to said heart after an AV delay following a sensed atrial event; means for controlling said means for supplying said ventricular pulse for operating said pacemaker in a DDD mode when said sensed atrial event occurs after a point in time SSI-AVmin, operating said pacemaker at a highest synchronous rate corresponding to said SSI when said sensed atrial event occurs between points in time SSI-AVmin and SSI-AVmax, and causing no ventricular stimulation pulse to be supplied when said sensed atrial event occurs before said point in time SSI-AVmax; an AV control unit in said means for controlling, said AV control unit having an input connected to said means for sensing an atrial event for normally generating a pulse upon the occurrence of each sensed atrial event for initiating supply of a ventricular pulse to said heart; an SSI calculator in said means for controlling, said SSI calculator having an input connected to said means for sensing a ventricular event, said output of said SSI calculator assuming a first logic state for a period commencing with the occurrence of a ventricular event and concluding after said smallest synchronous interval, said output of said SSI calculator thereafter switching to a second logic state; a flip-flop having a set input connected to the output of said AV control unit for setting said flip-flop to said second logic state upon the occurrence of said output pulse from said AV control unit; and logic means having inputs respectively connected to the outputs of said flip-flop and said SSI calculator for generating said ventricular pulse at an output of said logic means when both outputs of said flip-flop and said SSI calculator assumes said second logic state.

Claim 4

An atrial-controlled heart pacemaker operable with a maximum AV delay (AVmax), a minimum AV delay (AVmin) and a smallest synchronous interval (SSI) between two ventricular stimulation pulses comprising; means for sensing an atrial event in said heart; means for sensing a ventricular event in said heart; means for supplying a ventricular pulse to said heart after an AV delay following a sensed atrial event; means for controlling said means for supplying said ventricular pulse for operating said pacemaker in a DDD mode when said sensed atrial event occurs after a point in time SSI-AVmin, operating said pacemaker at a highest synchronous rate corresponding to said SSI when said sensed atrial event occurs between points in time SSI-AVmin and SSI-AVmax, and causing no ventricular stimulation pulse to be supplied when said sensed atrial event occurs before said point in time SSI-AVmax; an AV control unit in said means for controlling, said AV control unit having an input connected to said means for sensing an atrial event for normally generating a pulse upon the occurrence of each sensed atrial event for initiating supply of a ventricular pulse to said heart; an SSI calculator in said means for controlling, said SSI calculator having an input connected to said means for sensing a ventricular event, said output of said SSI calculator assuming a first logic state for a period commencing with the occurrence of a ventricular event and concluding after said smallest synchronous interval, said output of said SSI calculator thereafter switching to a second logic state; a flip-flop having a set input connected to the output of said AV control unit for setting said flip-flop to said second logic state upon the occurrence of said output pulse from said AV control unit; and logic means having inputs respectively connected to the outputs of said flip-flop and said SSI calculator for generating said ventricular pulse at an output of said logic means when both outputs of said flip-flop and said SSI calculator assumes said second logic state.

Claim 5

An atrium control heart pacemaker as claimed in claim 2, wherein said flip-flop has a reset input connected to said output of said logic means for returning said output of said flip-flop to said first logic state upon the generation of said ventricular pulse.