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US4701922A
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Integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1985-08-26
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Granted: 1987-10-20
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Expires: 2005-08-26
Abstract
Abstract An integrated circuit device comprises combinational circuits and sequential circuits. Each of the sequential circuits is provided with a (common) input control signal terminal for controlling the entry of main input terminal signals into the sequential circuit, a test data input/output terminal, a read/write signal terminal for controlling the transfer of the test data, and a latch circuit. The integrated circuit device is partitioned into sequential circuit groups, and combinational circuit groups used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers. Test data are written into and read out from the sequential circuit groups under control of read/write signal lines through bus lines dedicated to testing. Thus, a higher fault-coverage ratio can be easily obtained with a smaller number of steps and a small test circuit area.
Inventors
- 👤 Shigeo Kuboki
- 👤 Ikuro Masuda
- 👤 Toshiaki Masuda
- 👤 Terumine Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G11; G11C; G11C7/00; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
148 words
An integrated semiconductor circuit device comprising: a combinational circuit group; a sequential circuit group coupled to inputs of the combinational circuit group, wherein each sequential circuit within said sequential circuit group comprises: a master flip-flop circuit; a slave latch circuit; input terminals to receive a main input signal; a common input control signal terminal coupled to means within said sequential circuit to conrol entry of the main input signals into said sequential circuit; a test data terminal coupled to means within said sequential circuit to provide a testing function for said sequential circuit; a read terminal and/or a write terminal coupled to means within said sequential circuit for controlling transfer of test data generated in said sequential circuit during said testing function; and a latch signal terminal coupled to means within said sequential circuit for providing a shift clock to said sequential circuit to scan-out said test data.
Claim 2
Dependent Claim
148 words
An integrated semiconductor circuit device comprising: a combinational circuit group; a sequential circuit group coupled to inputs of the combinational circuit group, wherein each sequential circuit within said sequential circuit group comprises: a master flip-flop circuit; a slave latch circuit; input terminals to receive a main input signal; a common input control signal terminal coupled to means within said sequential circuit to conrol entry of the main input signals into said sequential circuit; a test data terminal coupled to means within said sequential circuit to provide a testing function for said sequential circuit; a read terminal and/or a write terminal coupled to means within said sequential circuit for controlling transfer of test data generated in said sequential circuit during said testing function; and a latch signal terminal coupled to means within said sequential circuit for providing a shift clock to said sequential circuit to scan-out said test data.
Claim 3
Dependent Claim
29 words
An integrated semiconductor circuit device according to claim 1, wherein scan-in of the test data is effected through a bus-like test data line connected to said test data line.
Claim 4
Dependent Claim
33 words
An integrated semiconductor circuit device according to claim 2, wherein the scan-out of test data is effected through a bus-like test data line connected to a data output terminal of the latch circuit.
Claim 5
Dependent Claim
39 words
An integrated semiconductor circuit device according to claim 3, wherein said input control signal terminal of the flip-flops and said latch timing signal terminal for the latch circuits, in all of the sequential circuits, are connected in common, respectively.
Claim 6
Dependent Claim
53 words
An integrated semiconductor circuit device according to claim 2, wherein said sequential circuit group is divided into flip-flop groups by means of address, and either the read or write terminal of each flip-flop is connected in common in each flip-flop group, or the test data terminal of each flip-flop is connected in common.
Claim 7
Dependent Claim
39 words
An integrated semiconductor circuit device according to claim 5, wherein said input control signal terminal of the flip-flops and said latch timing signal terminal for the latch circuits, in all of the sequential circuits, are connected in common, respectively.
Claim 8
Dependent Claim
57 words
An integrated semiconductor circuit device according to claim 2, wherein said sequential circuit group is divided into latch groups by means of address, and either the read or write signal terminal of each latch is connected in common in each latch group, or each input terminal and each output terminal of each latch is connected in common.
Claim 9
Dependent Claim
39 words
An integrated semiconductor circuit device according to claim 2, wherein said input control signal terminal of the flip-flops and said latch timing signal terminal for the latch circuits, in all of the sequential circuits, are connected in common, respectively.
Claim 10
Dependent Claim
33 words
An integrated semiconductor circuit device according to claim 1, wherein the scan-out of test data is effected through a bus-like test data line connected to a data output terminal of the latch circuit.
Claim 11
Dependent Claim
53 words
An integrated semiconductor circuit device according to claim 9, wherein said sequential circuit group is divided into flip-flop groups by means of address, and either the read or write terminal of each flip-flop is connected in common in each flip-flop group, or the test data terminal of each flip-flop is connected in common.
Claim 12
Dependent Claim
57 words
An integrated semiconductor circuit device according to claim 9, wherein said sequential circuit group is divided into latch groups by means of address, and either the read or write signal terminal of each latch is connected in common in each latch group, or each input terminal and each output terminal of each latch is connected in common.
Claim 13
Dependent Claim
39 words
An integrated semiconductor circuit device according to claim 9, wherein said input control signal terminal of the flip-flops and said latch timing signal terminal for the latch circuits, in all of the sequential circuits, are connected in common, respectively.
Claim 14
Dependent Claim
39 words
An integrated semiconductor circuit device according to claim 1, wherein said input control signal terminal of the flip-flops and said latch timing signal terminal for the latch circuits, in all of the sequential circuits, are connected in common, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |