US4689581A
Expired / Lapsed
US
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Integrated circuit phase locked loop timing apparatus
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1984-11-02
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Granted: 1987-08-25
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Expires: 2004-11-02
Abstract
Abstract An integrated circuit device includes a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are necessary. The phase locked loop includes a convertor and filter circuit (11), the convertor (14) including two transistor current sources (19,24) whose current magnitude is determined by a current reference circuit (13) including current mirror transistors (28, 31). The current sources (19, 24) are controlled by increase and decrease output signals from a phase and frequency comparator (7) such that the output of the convertor (14) depends upon the mark space ratio of the comparator output signals. The output of the convertor (14) is filtered and then fed as a control voltage to a voltage controlled oscillator (12). The oscillator output is fed by way of a divider to the phase comparator (7) and also provides the high frequency input timing signal for a logic device, such as a microcomputer (2). As the timing apparatus is fabricated using MOS technology, it is not possible to forecast its performance accurately. Surprisingly, it has been found that the timing apparatus of the invention is capable of exhibiting closed loop stability without further trimming. However, to ensure that such closed loop stability can always be obtained, additional components, for varying the parameters of the circuits may be provided, said components being connectible into the circuit by programmable switches, such as laser fuses (as 33, 42).
Inventors
- 👤 Gerald R. Talbot
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:05
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
271 words
An integrated circuit device comprising a logic device, a plurality of input pins connected to said logic device, a plurality of output pins connected to said logic device, and a timing apparatus for said logic device having an input connected to one of said input pins for receiving an input clock signal and an output connected to supply an output timing signal to said logic device, wherein both said logic device and said timing apparatus are completely formed on a common single chip, said timing apparatus comprising a phase locked loop arranged to produce said output timing signal whose frequency is a multiple of that of said received input clock signal, wherein said phase locked loop comprises: comparator means having a first input to which said received input clock signal is applied, a second input, and two outputs on which comparison signals are provided; a divider having an input connected to receive said output timing signal and an output connected to said second input of said comparator means, said divider being arranged to divide the frequency of said output timing signal by a predetermined integer; convertor and filter means connected to receive said comparison signals and arranged to generate a voltage signal whose magnitude is determined by said comparison signals; and a voltage controlled oscillator arranged to be controlled by said voltage signal to produce said output timing signal at its output, the output of said voltage controlled oscillator being connected to said input of said divider, and wherein the output of said voltage controlled oscillator is also directly connected to said logic device to supply said output timing signal thereto.
Claim 2
Dependent Claim
271 words
An integrated circuit device comprising a logic device, a plurality of input pins connected to said logic device, a plurality of output pins connected to said logic device, and a timing apparatus for said logic device having an input connected to one of said input pins for receiving an input clock signal and an output connected to supply an output timing signal to said logic device, wherein both said logic device and said timing apparatus are completely formed on a common single chip, said timing apparatus comprising a phase locked loop arranged to produce said output timing signal whose frequency is a multiple of that of said received input clock signal, wherein said phase locked loop comprises: comparator means having a first input to which said received input clock signal is applied, a second input, and two outputs on which comparison signals are provided; a divider having an input connected to receive said output timing signal and an output connected to said second input of said comparator means, said divider being arranged to divide the frequency of said output timing signal by a predetermined integer; convertor and filter means connected to receive said comparison signals and arranged to generate a voltage signal whose magnitude is determined by said comparison signals; and a voltage controlled oscillator arranged to be controlled by said voltage signal to produce said output timing signal at its output, the output of said voltage controlled oscillator being connected to said input of said divider, and wherein the output of said voltage controlled oscillator is also directly connected to said logic device to supply said output timing signal thereto.
Claim 3
Dependent Claim
54 words
An integrated circuit device according to claim 1 wherein said comparator means is a phase and frequency comparator and is arranged to produce first and second comparison output signals indicating a difference in either phase or frequency between the input clock signal and the divided output timing signal and the direction of this difference.
Claim 4
Dependent Claim
46 words
An integrated circuit device according to claim 2 wherein said convertor and filter means comprises at least one current source arranged to be controlled by said comparison signals and a current reference circuit arranged to determine the magnitude of the current produced by said current source.
Claim 5
Dependent Claim
100 words
An integrated circuit device according to claim 3 wherein said convertor and filter means comprises first and second current sources, said first current source being controlled by said first comparison signal, said second current source being controlled by said second comparison signal, each of said first and second current sources comprising a transistor and wherein said current reference circuit includes first and second current mirror transistors, each corresponding to a respective one of said first and second current source transistors, each current mirror transistor being arranged to determine the magnitude of the current produced by its corresponding current source transistor.
Claim 6
Dependent Claim
48 words
An integrated circuit device according to claim 4 wherein said current reference circuit is arranged to generate a predetermined reference voltage for determining the current flowing in each of the first and second current mirror transistors and hence in each of the first and second current source transistors.
Claim 7
Dependent Claim
45 words
An integrated circuit device according to claim 5 wherein said predetermined reference voltage is generated at a node connectible to the voltage supply by way of a circuit for determining said predetermined reference voltage, said circuit including a plurality of components connectible by programmable switches.
Claim 8
Dependent Claim
14 words
An integrated circuit device according to claim 6 wherein said programmable switches are fuses.
Claim 9
Dependent Claim
114 words
An integrated circuit device according to claim 1 wherein said convertor and filter means comprises a convertor coupled to receive said comparison signals and to produce a plurality of current pulses whose frequency is determined by said comparison signals, and a filter coupled to receive said current pulses and produce a dc output voltage whose magnitude is determined by said comparison signals, said filter having an input for receiving said current pulses, a MOS capacitor connected to said input, a transistor biased to operate as a resistor connected in series with said capacitor and to ground such that a series RC connection couples said input to ground, and an output connected to said capacitor.
Claim 10
Dependent Claim
267 words
An integrated circuit device comprising a logic device, a plurality of input pins connected to said logic device, a plurality of output pins connected to said logic device, and a timing apparatus for said logic device having an input connected to one of said input pins for receiving an input clock signal and an output connected to supply an output timing signal to said logic device, wherein both said logic device and said timing apparatus are completely formed on a common single chip, said timing apparatus comprising a phase locked loop arranged to produce said output timing signal whose frequency is a multiple of that of said received input clock signal, wherein said phase locked loop consists essentially of: a comparator having a first input to which said received input clock signal is applied, a second input connected to the output of a divider arranged to divide the frequency of the output timing signal by a predetermined integer, and two outputs on which comparison signals are produced; filter means coupled to receive current pulses derived from said comparison signals and to produce a dc output voltage whose magnitude is determined by said comparison signals; and a voltage controlled oscillator arranged to be controlled by said dc output voltage to produce said output timing signal, wherein said filter comprises an input for receiving said current pulses, a MOS capacitor connected to said input, a transistor biased to operate as a resistor connected in series with said capacitor and to ground such that a series RC connection couples said input to ground, and an output connected to said capacitor.
Claim 11
Dependent Claim
267 words
An integrated circuit device comprising a logic device, a plurality of input pins connected to said logic device, a plurality of output pins connected to said logic device, and a timing apparatus for said logic device having an input connected to one of said input pins for receiving an input clock signal and an output connected to supply an output timing signal to said logic device, wherein both said logic device and said timing apparatus are completely formed on a common single chip, said timing apparatus comprising a phase locked loop arranged to produce said output timing signal whose frequency is a multiple of that of said received input clock signal, wherein said phase locked loop consists essentially of: a comparator having a first input to which said received input clock signal is applied, a second input connected to the output of a divider arranged to divide the frequency of the output timing signal by a predetermined integer, and two outputs on which comparison signals are produced; filter means coupled to receive current pulses derived from said comparison signals and to produce a dc output voltage whose magnitude is determined by said comparison signals; and a voltage controlled oscillator arranged to be controlled by said dc output voltage to produce said output timing signal, wherein said filter comprises an input for receiving said current pulses, a MOS capacitor connected to said input, a transistor biased to operate as a resistor connected in series with said capacitor and to ground such that a series RC connection couples said input to ground, and an output connected to said capacitor.
Claim 12
Dependent Claim
34 words
An integrated circuit device according to claim 9, wherein said filter means further comprises one or more transistor means connectible by way of programmable switches whereby the parameters of the filter may be varied.
Claim 13
Dependent Claim
14 words
An integrated circuit device according to claim 10, wherein said programmable switches comprise fuses.
Claim 14
Dependent Claim
53 words
An integrated circuit device according to claim 10, wherein said comparator is a phase and frequency comparator and is arranged to produce first and second comparison output signals indicating a difference in either phase or frequency between the input clock signal and the divided output timing signal and the direction of this difference.
Claim 15
Dependent Claim
106 words
An integrated circuit device according to claim 12, wherein said phase locked loop further includes a convertor arranged to receive said comparison signals and to produce a plurality of current pulses whose frequency is determined by said comparison signals, said filter means being coupled to receive said current pulses, and wherein said convertor comprises first and second current source transistors controlled by said comparison signals, and first and second current mirror transistors each corresponding to a respective one of said first and second current source transistors, each current mirror transistor being arranged to determine the magnitude of the current produced by its corresponding current source transistor.
Claim 16
Dependent Claim
31 words
An integrated circuit device according to claim 1 or 9 wherein said voltage controlled oscillator includes at least one capacitive circuit comprising a current source transistor coupled to a MOS capacitor.
Claim 17
Dependent Claim
267 words
An integrated circuit device comprising a logic device, a plurality of input pins connected to said logic device, a plurality of output pins connected to said logic device, and a timing apparatus for said logic device having an input connected to one of said input pins for receiving an input clock signal and an output connected to supply an output timing signal to said logic device, wherein both said logic device and said timing apparatus are completely formed on a common single chip, said timing apparatus comprising a phase locked loop arranged to produce said output timing signal whose frequency is a multiple of that of said received input clock signal, wherein said phase locked loop consists essentially of: a comparator having a first input to which said received input clock signal is applied, a second input connected to the output of a divider arranged to divide the frequency of the output timing signal by a predetermined integer, and two outputs on which comparison signals are produced; filter means coupled to receive pulses derived from said comparison signals and to produce a dc output voltage whose magnitude is determined by said comparison signals; and a voltage controlled oscillator arranged to be controlled by said dc output signal to produce said output timing signal, wherein said voltage controlled oscillator comprises an input to receive said dc output voltage, an output, and switchable means for producing oscillations at a frequency determined by the magnitude of said output voltage, said voltage controlled oscillator further including at least one capacitive circuit comprising a current source transistor coupled to a MOS capacitor.
Claim 18
Dependent Claim
267 words
An integrated circuit device comprising a logic device, a plurality of input pins connected to said logic device, a plurality of output pins connected to said logic device, and a timing apparatus for said logic device having an input connected to one of said input pins for receiving an input clock signal and an output connected to supply an output timing signal to said logic device, wherein both said logic device and said timing apparatus are completely formed on a common single chip, said timing apparatus comprising a phase locked loop arranged to produce said output timing signal whose frequency is a multiple of that of said received input clock signal, wherein said phase locked loop consists essentially of: a comparator having a first input to which said received input clock signal is applied, a second input connected to the output of a divider arranged to divide the frequency of the output timing signal by a predetermined integer, and two outputs on which comparison signals are produced; filter means coupled to receive pulses derived from said comparison signals and to produce a dc output voltage whose magnitude is determined by said comparison signals; and a voltage controlled oscillator arranged to be controlled by said dc output signal to produce said output timing signal, wherein said voltage controlled oscillator comprises an input to receive said dc output voltage, an output, and switchable means for producing oscillations at a frequency determined by the magnitude of said output voltage, said voltage controlled oscillator further including at least one capacitive circuit comprising a current source transistor coupled to a MOS capacitor.
Claim 19
Dependent Claim
32 words
An integrated circuit device according to claim 15 further comprising means for varying the time constant of said capacitive circuit whereby the center frequency of said voltage controlled oscillator may be varied.
Claim 20
Dependent Claim
37 words
An integrated circuit device according to claim 16 wherein said means for varying the time constant of the capacitive circuit includes at least one further MOS capacitor connected to said capacitive circuit by way of programmable switches.
Claim 21
Dependent Claim
37 words
An integrated circuit device according to claim 17 wherein said means for varying the time constant of the capacitive circuit includes one or more transistor means connectible in parallel with said current source transistor by programmable switches.
Claim 22
Dependent Claim
16 words
An integrated circuit device according to claim 17 or 18, wherein said programmable switches are fuses.
Claim 23
Dependent Claim
153 words
An integrated circuit device according to claim 15 wherein said switchable means of the voltage controlled oscillator comprises two switching transistors, the current path of each of said swiitching transistors being connected to a node, and a Schmitt trigger having an input connected to said node and an output forming the output of said voltage controlled oscillator, the output of said Schmitt trigger also being coupled to the gates of said switching transistors, and wherein said MOS capacitor is connected to said node, said voltage controlled oscillator further comprising two current source transistors, each being connected to a respective one of said switching transistors, and two current mirror transistors, each current mirror transistor being connected to the input of the voltage controlled oscillator and to a respective one of said current source transistors such that the current flowing in each current source transistor is determined by the magnitude of said dc output voltage.
Claim 24
Dependent Claim
214 words
An integrated circuit device according to claim 15, wherein the switchable means of the voltage controlled oscillator comprises: first and second pairs of switching transistors, the current paths of the two transistors in each pair being connected together at a node, and two NAND gates, each NAND gate having first and second inputs and an output, the first input of each NAND gate being connected to the said node between a respective one of said pairs of switching transistors, and the second input of each NAND gate being connected to the output of the other NAND gate, the output of each NAND gate also being connected to the gates of the transistors of the pair of switching transistors other than the pair to which its first input is connected, the voltage controlled oscillator further comprising two MOS capacitors, each MOS capacitor being connected to the node of a respective pair of switching transistors, said current source transistor being coupled to each of said MOS capacitors by way of the respective pair of switching transistors, said current source transistor being connected to the input of the voltage controlled oscillator and to said pairs of switching transistors such that the current flowing in said switching transistors is determined by the magnitude of said dc output voltage.
Claim 25
Dependent Claim
16 words
An integrated circuit device as claimed in claim 15, wherein said logic device is a microcomputer.
Claim 26
Independent Claim
180 words
A method of supplying timing signals to an integrated circuit logic device employing a timing apparatus formed together with the logic device on a common single chip, the method comprising the steps of: applying a low frequency clock signal to an input of said timing apparatus, the timing apparatus being arranged to generate a high frequency timing signal at its output having a frequency which is a multiple of that of said clock signal, dividing the frequency of said high frequency timing signal by a predetermined integer, comparing the divided frequency with the frequency of the clock signal, generating an increase or a decrease comparison signal where the clock signal frequency is respectively greater than or less than said divided frequency, generating a dc voltage whose magnitude is determined by said comparison signals, and generating said high frequency timing signal at the output of a voltage controlled oscillator controlled by said dc voltage, wherein said high frequency timing signal at the output of said voltage controlled oscillator is connected directly to said logic device to form the timing signal therefor.
Claim 27
Independent Claim
180 words
A method of supplying timing signals to an integrated circuit logic device employing a timing apparatus formed together with the logic device on a common single chip, the method comprising the steps of: applying a low frequency clock signal to an input of said timing apparatus, the timing apparatus being arranged to generate a high frequency timing signal at its output having a frequency which is a multiple of that of said clock signal, dividing the frequency of said high frequency timing signal by a predetermined integer, comparing the divided frequency with the frequency of the clock signal, generating an increase or a decrease comparison signal where the clock signal frequency is respectively greater than or less than said divided frequency, generating a dc voltage whose magnitude is determined by said comparison signals, and generating said high frequency timing signal at the output of a voltage controlled oscillator controlled by said dc voltage, wherein said high frequency timing signal at the output of said voltage controlled oscillator is connected directly to said logic device to form the timing signal therefor.
Claim 28
Dependent Claim
47 words
A method according to claim 23 further comprising determining the operating speed of said logic device, and selecting said predetermined integer by which said high frequency timing signal is divided such that the frequency of said high frequency timing signal is matched to the said operating speed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-24 | 1991-02-23 | 1991-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-24 | 1995-02-23 | 1995-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-24 | 1999-02-23 | 1999-08-25 | $7700.00 | Window Closed / Lapsed |