US4665484A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shared memory multiprocessing system & method
Assignee: NEC Corp
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Filing: 1984-11-14
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Granted: 1987-05-12
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Expires: 2004-11-14
Abstract
Abstract When a first program executed on a first processor of a plurality of processors of a multiprocessing system intends to lock a given shared resource of a main memory in order to use same, if the desired resource is in use by a second program executed on a second processor, the first processor awaits an unlock signal which indicates that one of the shared resources is released for use. The first processor responds to the unlock signal and checks whether or not the desired resource is available. If not available, the first program again awaits the reception of the unlock signal, while if available, the first program accesses the desired resource to use same.
Inventors
- 👤 Shinji Nanba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:15
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30076; G06F9/30087
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
108 words
A hardware arrangement for controlling a multi-processing system wherein a plurality of programs are processed simultaneously by two or more processors which share in common a main memory, and wherein said processors lock a shared resource within said main memory, said hardware arrangement comprising: a means for performing a logical OR, said means having a plurality of input terminals coupled to an output terminal of each of the processors and having an output terminal coupled to an input terminal of each of the processors, said means for performing a logical OR being supplied with an unlock signal which one of the processors produces when unlocking the shared resource.
Claim 2
Dependent Claim
108 words
A hardware arrangement for controlling a multi-processing system wherein a plurality of programs are processed simultaneously by two or more processors which share in common a main memory, and wherein said processors lock a shared resource within said main memory, said hardware arrangement comprising: a means for performing a logical OR, said means having a plurality of input terminals coupled to an output terminal of each of the processors and having an output terminal coupled to an input terminal of each of the processors, said means for performing a logical OR being supplied with an unlock signal which one of the processors produces when unlocking the shared resource.
Claim 3
Independent Claim
185 words
A method of controlling a multiprocessing system wherein a plurality of programs are processed simultaneously by two or more processors which share in common a main memory, and wherein said processors lock a shared resource within said main memory by the steps of: (a) obtaining a right to use a common bus; (b) fetching the operand of a lock instruction; (c) determining whether the operand satisfies a first predetermined condition; (d) abandoning the right to use the common bus if the operand does not satisfy said first predetermined condition, and waiting until one of the processors produces an unlock signal; (e) repeating the steps (a) through (c) if the unlock signal is produced; (f) writing a first predetermined code into said operand if said operand satisfies said first predetermined condition; and (g) abandoning the right to use the common bus; and wherein said processors unlock the shared resource by the steps of: (h) obtaining the right to use the common bus; (i) writing a second predetermined code into said operand; (j) producing the unlock signal; and (k) abandoning the right to use the common bus.
Claim 4
Independent Claim
185 words
A method of controlling a multiprocessing system wherein a plurality of programs are processed simultaneously by two or more processors which share in common a main memory, and wherein said processors lock a shared resource within said main memory by the steps of: (a) obtaining a right to use a common bus; (b) fetching the operand of a lock instruction; (c) determining whether the operand satisfies a first predetermined condition; (d) abandoning the right to use the common bus if the operand does not satisfy said first predetermined condition, and waiting until one of the processors produces an unlock signal; (e) repeating the steps (a) through (c) if the unlock signal is produced; (f) writing a first predetermined code into said operand if said operand satisfies said first predetermined condition; and (g) abandoning the right to use the common bus; and wherein said processors unlock the shared resource by the steps of: (h) obtaining the right to use the common bus; (i) writing a second predetermined code into said operand; (j) producing the unlock signal; and (k) abandoning the right to use the common bus.
References Cited (Backward Citations)
US3896418A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-11 | 1990-11-10 | 1991-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-11 | 1994-11-10 | 1995-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-11 | 1998-11-10 | 1999-05-12 | $7700.00 | Window Closed / Lapsed |