Error-correcting circuit having a reduced syndrome word

Claim 2

An integrated circuit error-correction circuit for correcting up to one error in a data field carried by M data signals on a set of data lines (110) disposed in a first region of said integrated circuit, each of said set of data lines having a sequential binary data address representative of the location of that data line within the set of data lines; said circuit further comprising a set of parity lines (120) carrying a set of K parity signals formed in a predetermined manner from a set of input data signals where K is the least integer which satisfies the equation 2 K ≧M+K+1; parity means for combining said set of parity signals and said data signals in a predetermined manner to generate a binary syndrome word (151) having K-1 bits; and means (170) connected to the output of said parity means, for correcting a single data signal located at a binary error address specified by the contents of said syndrome word.

Claim 3

An integrated circuit according to claim 1, in which said syndrome word is equal to a binary data address of magnitude less than or equal to M.

Claim 4

An integrated circuit according to claim 2, further comprising first syndrome comparison means (150) for comparing a first selected subset of contiguous bits of said syndrome word with a counterpart subset of field-identification bits, received from a selection stage (135), defining a subset of said data field and generating therefrom an error correction enabling signal on an output line (159).

Claim 5

An integrated circuit according to claim 3, in which said first syndrome comparing and generating means further combines said parity check bit with other signals to inhibit error correction when said parity check bit (P 4 ) indicates an error in said parity signals.

Claim 6

An integrated circuit according to claim 3, further comprising second syndrome decoding means for decoding a second selected subset of contiguous bits from said syndrome word and combining said second subset of bits with said error correction enabling signal to control a selected one of a set of data inversion circuits.

Claim 7

An integrated circuit according to claim 2, in which said means for correcting a data signal responds to a predetermined one of said binary data addresses to inhibit error correction operation.

Claim 8

An integrated circuit according to claim 1, in which said parity means combines said K parity signals to form a parity check bit indicative of the parity of said K parity signals.

Claim 9

An integrated circuit according to claim 1, in which M=2 K-1 , whereby said syndrome word points to errors within said data field only.

Claim 10

An integrated circuit error-correction circuit for correcting up to one error in a data field carried by M data signals on a set of data lines disposed in a first region of said integrated circuit, each of said set of data lines having a sequential binary data address representative of the location of that data line within the set of data lines; said integrated circuit further comprising a set of parity lines carrying a set of K parity signals formed in a predetermined manner from a set of input data signals; parity means for combining said set of parity signals and said data signals in a predetermined manner to generate a binary syndrome word (151) and a parity check bit dependent only on said parity signals; and means (170) connected to the output of said parity means, for correcting a single data signal located at a binary error address specified by the contents of said syndrome word.

Claim 11

An integrated circuit error-correction circuit for correcting up to one error in a data field carried by M data signals on a set of data lines disposed in a first region of said integrated circuit, each of said set of data lines having a sequential binary data address representative of the location of that data line within the set of data lines; said integrated circuit further comprising a set of parity lines carrying a set of K parity signals formed in a predetermined manner from a set of input data signals; parity means for combining said set of parity signals and said data signals in a predetermined manner to generate a binary syndrome word (151) and a parity check bit dependent only on said parity signals; and means (170) connected to the output of said parity means, for correcting a single data signal located at a binary error address specified by the contents of said syndrome word.

Claim 12

An integrated circuit according to claim 9, in which said means for correcting a single data signal receives said parity check bit as input and inhibits error correction in response to a predetermined state of said parity check bit, whereby only errors within said data field may be corrected without inhibition.

Claim 13

An integrated circuit error-correction circuit for correcting up to one error in a data field carried by M data signals on a set of data lines (110) disposed in a first region of said integrated circuit, each of said set of data lines having a sequential binary data address representative of the location of that data line within the set of data lines; said integrated circuit further comprising a set of parity lines carrying a set of K parity signals formed in a predetermined manner from a set of input data signals where K is the least integer which satisfies the equation 2 K ≧M+K+1, said set of parity lines being disposed within a second region, whereby said parity lines and data lines are not intermingled; parity means for combining said set of parity signals and said data signals in a predetermined manner to generate a binary syndrome word (151) in which a seleted set of intermediate data parity signals (141) is formed by grouping said data signals in powers of two and in which each of said set of intermediate signals is combined with a counterpart parity signal to form a bit of said binary syndrome word (151); and means (170) connected to the output of said parity means, for correcting a single data signal located at a binary error address specified by the contents of said syndrome word.

Claim 14

An integrated circuit error-correction circuit for correcting up to one error in a data field carried by M data signals on a set of data lines (110) disposed in a first region of said integrated circuit, each of said set of data lines having a sequential binary data address representative of the location of that data line within the set of data lines; said integrated circuit further comprising a set of parity lines carrying a set of K parity signals formed in a predetermined manner from a set of input data signals where K is the least integer which satisfies the equation 2 K ≧M+K+1, said set of parity lines being disposed within a second region, whereby said parity lines and data lines are not intermingled; parity means for combining said set of parity signals and said data signals in a predetermined manner to generate a binary syndrome word (151) in which a seleted set of intermediate data parity signals (141) is formed by grouping said data signals in powers of two and in which each of said set of intermediate signals is combined with a counterpart parity signal to form a bit of said binary syndrome word (151); and means (170) connected to the output of said parity means, for correcting a single data signal located at a binary error address specified by the contents of said syndrome word.

Claim 15

An integrated circuit according to claim 11, in which said set of intermediate signals and said syndrome word each have K-1 elements, whereby said syndrome word has insufficicant bits to point to errors in both data and parity signals.