Computer speed control

Claim 1

A slow down circuit for a digital computer having a microprocessor which has a microprocessor ready line which enables said microprocessor when impressed with a first logic level voltage and disables the microprocessor when impressed with a second logic level voltage, an address bus, a data bus and a clock pulse generator for producing a clock pulse train, said slow down circuit comprising: (a) address decode logic means connected to said address bus and said clock pulse generator for producing a clock pulse train when predetermined bit patterns appear on said address bus, said predetermined bit patterns representing special computer functions which require the computer to operate at normal speed; (b) inhibit signal generating means connected to said address bus and said address decode logic means for producing an inhibit signal when said predetermined bit patterns appear on said address bus and in the presence of said clock pulse train from said address decode logic means; (c) slow down signal generating means connected to said address bus and said data bus for generating a bi-level signal; and (d) combining means having input terminals connected to said inhibit signal generating means and said slow down signal generating means and an output terminal connected to said microprocessor ready line for combining said inhibit signal and said bi-level signal to produce a control signal; wherein, said control signal has said first and second logic level voltages and wherein said control signal is at said first logic level voltage for enabling said ready line in the presence of said special computer functions and alternately switches between said first logic level voltage and said second logic level voltage in the absence of said special computer functions, said second logic level voltage causing a disabling of said microprocessor to thereby slow down the operation of said microprocessor.