Multimode pulse generator

Claim 2

A pulse generator for providing output pulse waveform cycles having an expanded resolution period and phase synchronization to external trigger pulses from an external trigger source, characterized by: memory means for storing predetermined pulse output waveforms; latch means receiving the external trigger pulses and latched thereby for providing outputs; means for providing delay data; clock means including an internal clock having delay line means connected to the delay data means and responsive to the data therefrom for providing delay outputs, and first gating means connected to the delay line means and to the latch means for gating the latch outputs and the delay outputs and for providing clock outputs in phase synchronization with the latch outputs; and first counter means connected to the latch means, the clock means and the memory means, and responsive to the outputs from the latch means and the clock means for addressing the memory means, whereby the memory means provides predetermined stored output pulse waveform cycles, each cycle having a maximum of three periods, one of which is the expanded resolution period.

Claim 3

A pulse generator as described by claim 1, further characterized by: the clock outputs in phase synchronization with the latch outputs being fed back to the delay line means.

Claim 4

A pulse generator as described by claim 1, further characterized by: second counter means; first switching means operative for connecting the second counter means to the first gating means, said second counter means counting the clock outputs from the first gating means and providing a predetermined count of the clock outputs; and second gating means connected to the second counter means and to the first counter means for gating the predetermined count of the clock outputs to the first counter means.

Claim 5

A pulse generator as described by claim 3, further characterized by: means for providing a dividing output; and the second counter means connected to the dividing output means and responsive to the dividing output therefrom for providing a predetermined divided count of the clock outputs.

Claim 6

A pulse generator as described by claim 3, wherein the first counter means is characterized by: a first counter connected to the latch means and to the first gating means, and gated by the latch outputs from the latch means and clocked by the clock outputs from the first gating means for providing counting outputs; third gating means connected to the latch means and the first counter and responsive to the latch outputs or the counting outputs for providing a loading output; and a second counter connected to the third gating means and to the memory means and responsive to the loading output from the third gating means for counting from one output pulse waveform cycle to another and for addressing the memory means, whereupon the memory means provides the predetermined stored output pulse waveform cycles.

Claim 7

A pulse generator as described by claim 5, further characterized by: the second gating means being connected to the first counter and controlled by the counting outputs therefrom.

Claim 8

A pulse generator as described by claim 5, further characterized by: the second counter providing a clock output and an output signifying the end of an output pulse waveform cycle; a third counter connected to the second counter and responsive to the clock output therefrom for providing a termination output; fourth gating means connected to the third counter; second switching means operable for connecting the second counter to the fourth gating means; the fourth gating means being responsive to the termination output from the third counter and to the end cycle output from the second counter applied through the second switching means for providing a reset output; and the latch means connected to the fourth gating means and responsive to the reset output for being reset thereby.

Claim 9

A pulse generator as described by claim 1, further characterized by: converting means connected to the memory means for converting the output pulse waveform cycles provided thereby to monitor/test outputs.

Claim 10

A pulse generator as described by claim 3, further characterized by: an external clock for providing clock outputs; the first switching means operative for connecting the external clock to the second counter means and for disconnecting the internal clock therefrom; and said second counter means counting the clock outputs from the external clock and providing a predetermined count of the clock outputs.

Claim 11

A pulse generator as described by claim 7, characterized by: the second switching means operable for disconnecting the second counter from the fourth gating means, whereupon the end cycle output from said counter is prevented from being applied to the fourth gating means and said fourth gating means is prevented from providing the reset output.

Claim 12

A pulse generator as described by claim 1, characterized by: the latch means receiving an external trigger pulse and latched thereby for providing an output; and the first counter means being responsive to the output from the latch means and the clock outputs from the clock means for addressing the memory means to start an output pulse waveform cycle which has an immediate expanded resolution period and a memory output period following the expanded resolution period and lasting until the latch means receives another external trigger pulse to start another cycle.

Claim 13

A pulse generator as described by claim 1, characterized by: the latch means receiving an external trigger pulse and latched thereby for providing an output; and the first counter means being responsive to the output from the latch means and the clock outputs from the clock means for addressing the memory means to start an output pulse waveform cycle which has a first memory output period, and expanded resolution output period which is delayed from starting until the end of the first memory output period, and a last memory output period which starts at the end of the expanded resolution period and lasts until the latch means receives another external trigger pulse to start another cycle.

Claim 14

A pulse generator as described by claim 1, characterized by: the latch means receiving a first external trigger pulse for providing a first output and a second external trigger pulse for providing a second output; the first counter means being responsive to the first and second latch outputs for defining an internal period; and the first counter means being responsive to the latch outputs from the latch means and the clock outputs from the clock means for addressing the memory means to start an output pulse waveform cycle having a plurality of internal periods, with each of the internal periods having an immediate expanded resolution period and a memory output period following the expanded resolution period.

Claim 15

A pulse generator as described by claim 1, characterized by: an external clock for providing clock outputs; the latch means receiving an external pulse and latched thereby for providing an output; and the first counter means being responsive to the outputs from the external clock and the output from the latch means for addressing the memory means to provide output pulse waveform cycles having memory output periods occurring during the expanded resolution period.

Claim 16

A pulse generator for providing output pulse cycles having an expanded resolution output period and providing predetermined output pulse waveforms phase synchronized to external trigger pulses, characterized by: memory means for storing the predetermined output pulse waveforms; means for providing the external trigger pulses; latch means connected to the external trigger pulse means and being latched by a pulse received therefrom for providing an output; first counter means connected to the latch means and responsive to the output therefrom for providing an output; second counter means connected to the memory means for addressing said memory means; clock means connected to the latch means and responsive to the output therefrom for providing outputs in phase synchronization with the latch output; first gating means for connecting the latch means and the first counter means to the second counter means; second gating means for connecting the second counter means to the clock means; the second counter means being responsive to one of the outputs from the latch means and the first counter means applied through the first gating means for addressing the memory means to start a first memory output period in a pulse output cycle, said first memory output period lasting until a first output from the clock means is applied to the second counting means through the second gating means; the second counter means starting to count down from the end of the first memory output period to the beginning of a last memory output period when a second output from the clock means is applied to the second counter means through the second gating means, whereupon the memory means is addressed by the second counter means to start the last memory output period; the period between the end of the first memory output period and the beginning of the last memory output period being an expanded resolution output period; and the output pulse cycle remaining at the last memory output period until the latch means receives another pulse from the external trigger pulse means to start another output pulse cycle.

Claim 17

A pulse generator for providing output pulse cycles having an expanded resolution output period and providing predetermined output pulse waveforms phase synchronized to external trigger pulses, characterized by: memory means for storing the predetermined output pulse waveforms; means for providing the external trigger pulses; latch means connected to the external trigger pulse means and being latched by a pulse received therefrom for providing an output; first counter means connected to the latch means and responsive to the output therefrom for providing an output; second counter means connected to the memory means for addressing said memory means; clock means connected to the latch means and responsive to the output therefrom for providing outputs in phase synchronization with the latch output; first gating means for connecting the latch means and the first counter means to the second counter means; second gating means for connecting the second counter means to the clock means; the second counter means being responsive to one of the outputs from the latch means and the first counter means applied through the first gating means for addressing the memory means to start a first memory output period in a pulse output cycle, said first memory output period lasting until a first output from the clock means is applied to the second counting means through the second gating means; the second counter means starting to count down from the end of the first memory output period to the beginning of a last memory output period when a second output from the clock means is applied to the second counter means through the second gating means, whereupon the memory means is addressed by the second counter means to start the last memory output period; the period between the end of the first memory output period and the beginning of the last memory output period being an expanded resolution output period; and the output pulse cycle remaining at the last memory output period until the latch means receives another pulse from the external trigger pulse means to start another output pulse cycle.

Claim 18

A pulse generator for providing output pulse waveform cycles having an expanded resolution period and phase synchronization to external trigger pulses from an external trigger source, characterized by: memory means for storing predetermined pulse output waveforms; latch means receiving the external trigger pulses and latched thereby for providing outputs; clock means connected to the latch means and responsive to the outputs therefrom for providing clock outputs in phase synchronization with the latch outputs; counter means connected to the latch means, the clock means and the memory means, and responsive to the outputs from the latch means and the clock means for addressing the memory means, whereby the memory means provides predetermined stored output pulse waveform cycles, each cycle having a maximum of three periods, one of which is the expanded resolution period; the latch means receiving a first external trigger pulse for providing a first output and a second external trigger pulse for providing a second output; means for providing a period delay output; the counter means being responsive to the first and second latch means outputs for defining an internal period; and the counter means being responsive to the first and second latch outputs from the latch means, the period delay output and the clock outputs from the clock means for addressing the memory means to start an output pulse waveform cycle having a plurality of internal periods including a first memory output period occurring during a delay period defined by the period delay output, an expanded resolution period which starts at the end of the delay period, and a memory output period which starts at the end of the expanded resolution period.

Claim 19

A pulse generator for providing output pulse waveform cycles having an expanded resolution period and phase synchronization to external trigger pulses from an external trigger source, characterized by: memory means for storing predetermined pulse output waveforms; latch means receiving the external trigger pulses and latched thereby for providing outputs; clock means connected to the latch means and responsive to the outputs therefrom for providing clock outputs in phase synchronization with the latch outputs; counter means connected to the latch means, the clock means and the memory means, and responsive to the outputs from the latch means and the clock means for addressing the memory means, whereby the memory means provides predetermined stored output pulse waveform cycles, each cycle having a maximum of three periods, one of which is the expanded resolution period; the latch means receiving a first external trigger pulse for providing a first output and a second external trigger pulse for providing a second output; means for providing a period delay output; the counter means being responsive to the first and second latch means outputs for defining an internal period; and the counter means being responsive to the first and second latch outputs from the latch means, the period delay output and the clock outputs from the clock means for addressing the memory means to start an output pulse waveform cycle having a plurality of internal periods including a first memory output period occurring during a delay period defined by the period delay output, an expanded resolution period which starts at the end of the delay period, and a memory output period which starts at the end of the expanded resolution period.