US4597104A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selective call signal detection circuit for multi-channel access type radio receiving station
Assignee: Uniden Corp
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Filing: 1984-10-12
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Granted: 1986-06-24
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Expires: 2004-10-12
Abstract
Abstract A selective call signal detection circuit comprises a channel free/busy state detection circuit for scanning a plurality of communication channels to determine their respective free/busy states, a present-time channel free/busy state memory circuit for temporarily storing channel free/busy detection signals resulting from the aforementioned scanning of communication channels, a past-time channel free-busy state memory circuit for receiving into storage therein in the subsequent channel scanning cycle the channel free/busy detection signals of the previous scanning cycle formerly stored in the aforementioned present-time channel free/busy state memory circuit, and a comparison circuit for comparing the signals from the aforementioned present-time past-time channel free/busy state memory circuits thereby discriminating between a selective call signal addressed to a given receiving station and selective call signals addressed to other receiving stations. Since this selective call signal detection circuit permits quick discrimination between a channel in the state of normal communication and a channel in the state of selective call, it serves to enhance the efficiency of channel scanning.
Inventors
- 👤 Isao Ohki
- 👤 Yoshikazu Noritake
- 👤 Hitoshi Hachiga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:38
CPC Classifications
H; H04; H04W; H04W48/00; H04W48/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
257 words
In a selective call signal detection circuit for use in each of receiving stations sharing a plurality of communication channels for discrimination between a selective call signal addressed to itself and selective call signals addressed to other receiving stations, the improvement comprising: a channel free/busy state detection circuit for sequentially scanning said communication channels and determining "free" and "busy" states thereof and for sequentially issuing channel free/busy state detection signals, a present-time channel free/busy state memory circuit for sequentially memorizing in a first cycle of channel scanning said channel free/busy state detection signals issued sequentially from said channel free/busy state detection circuit, a past-time channel free/busy state memory circuit for memorizing therein channel free/busy state detection signals temporarily memorized in said present-time channel free/busy state memory circuit thereby allowing said signals memorized in said present-time channel free/busy state memory to be used in a second cycle of channel scanning as channel free/busy state detecting signals of said first cycle of channel scanning, and a past-time present-time channel free/busy state comparison circuit for comparing data on channel free/busy state from said past-time channel free/busy state memory circuit and data on channel free/busy state from said present-time channel free/busy state memory circuit with respect to each of said communication channels, said comparison circuit being adapted to issue a selective call signal detection signal when, in any of the channels, there occurs a change from the "free" state of channel in the first cycle of channel scanning to the "busy" state of channel in the second cycle of channel scanning.
Claim 2
Dependent Claim
257 words
In a selective call signal detection circuit for use in each of receiving stations sharing a plurality of communication channels for discrimination between a selective call signal addressed to itself and selective call signals addressed to other receiving stations, the improvement comprising: a channel free/busy state detection circuit for sequentially scanning said communication channels and determining "free" and "busy" states thereof and for sequentially issuing channel free/busy state detection signals, a present-time channel free/busy state memory circuit for sequentially memorizing in a first cycle of channel scanning said channel free/busy state detection signals issued sequentially from said channel free/busy state detection circuit, a past-time channel free/busy state memory circuit for memorizing therein channel free/busy state detection signals temporarily memorized in said present-time channel free/busy state memory circuit thereby allowing said signals memorized in said present-time channel free/busy state memory to be used in a second cycle of channel scanning as channel free/busy state detecting signals of said first cycle of channel scanning, and a past-time present-time channel free/busy state comparison circuit for comparing data on channel free/busy state from said past-time channel free/busy state memory circuit and data on channel free/busy state from said present-time channel free/busy state memory circuit with respect to each of said communication channels, said comparison circuit being adapted to issue a selective call signal detection signal when, in any of the channels, there occurs a change from the "free" state of channel in the first cycle of channel scanning to the "busy" state of channel in the second cycle of channel scanning.
Claim 3
Dependent Claim
56 words
A selective call signal detection circuit according to claim 1, wherein said channel free/busy detection circuit comprises a mixer adapted to establish a beat between locally oscillated signals from a local oscillation circuit and high-frequency receiving input signals and a noise detector for detecting channel free/busy state with respect to the intermediate frequency from said mixer.
Claim 4
Dependent Claim
88 words
A selective call signal detection circuit according to claim 2, which further comprises a channel scanning shift register for sequentially issuing locally oscillated selective signals with respect to said communication channels upon reception of signals resulting from inversion of clock pulses from a clock pulse generator and divided signals resulting from division of said clock pulses by the number of channels and means for receiving said locally oscillated selective signals from said channel scanning shift register and, in response thereto, forwarding preset frequencies to said local oscillation circuit.
Claim 5
Dependent Claim
36 words
A selective call signal detection circuit according to claim 1, wherein said present-time channel free/busy state memory circuit comprises a first shift register and said past-time channel free/busy state memory circuit comprises a second shift register.
Claim 6
Dependent Claim
57 words
A selective call signal detection circuit according to any one of claims 1-4, wherein said comparison circuit comprises an AND gate for receiving the output from said present-time channel free/busy state memory circuit and the output from said past-time channel free/busy state memory circuit and, in response thereto, issues an AND output as a selective call signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-23 | 1989-12-23 | 1990-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-23 | 1993-12-23 | 1994-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-23 | 1997-12-23 | 1998-06-24 | $7700.00 | Window Closed / Lapsed |