Method of making semiconductor integrated circuits having backside gettered with phosphorus

Claim 2

In a method of fabricating a semiconductor integrated circuit integrated at a top major surface of a semiconductor body, the step of: gettering the body with phosphorus by heating the body at an elevated temperature in an atmosphere containing phosphorus at a time when the top surface, but not the bottom surface, of the body is protected against the penetration of phosphorus by means of a sacrificial glass layer which has a sufficiently low phosphorus concentration that essentially no phosphorus diffuses from it into the body.

Claim 3

In a method of fabricating a semiconductor circuit including a plurality of transistors integrated at a top major surface of a silicon semiconductor body, the steps of: (a) forming polysilicon layer doped with arsenic or antimony upon the sidewalls and the bottom surfaces of apertures extending through an insulating layer coating the top surface, whereby the polysilicon layer makes contact, at the bottoom of each of the apertures, with at least first and second separated localized regions doped with arsenic or anitmony located at the top surface of the body, the first and second regions being terminal regions of first and second transistors, respectively; (b) depositing a sacrificial protective layer upon the polysilicon layer, to protect the top surface of the body against introduction of phosphorus; (c) gettering the semiconductor body by a heat treatment at a gettering temperature in an ambient atmosphere containing phosphorus at a time when the protective layer is present on the polysilicon layer, whereby phosphorus from the ambient enters into the silicon body through the bottom major surface of the body but not through the top major surface thereof.

Claim 4

In a method of fabricating a semiconductor circuit including a plurality of transistors integrated at a top major surface of a silicon semiconductor body, the steps of: (a) forming polysilicon layer doped with arsenic or antimony upon the sidewalls and the bottom surfaces of apertures extending through an insulating layer coating the top surface, whereby the polysilicon layer makes contact, at the bottoom of each of the apertures, with at least first and second separated localized regions doped with arsenic or anitmony located at the top surface of the body, the first and second regions being terminal regions of first and second transistors, respectively; (b) depositing a sacrificial protective layer upon the polysilicon layer, to protect the top surface of the body against introduction of phosphorus; (c) gettering the semiconductor body by a heat treatment at a gettering temperature in an ambient atmosphere containing phosphorus at a time when the protective layer is present on the polysilicon layer, whereby phosphorus from the ambient enters into the silicon body through the bottom major surface of the body but not through the top major surface thereof.

Claim 5

In the method of fabricating a semiconductor circuit according to claim 2, the steps recited in claim 2 followed by the steps of: removing the protective layer to expose the polysilicon layer; depositing a metal layer upon the polysilicon layer; and patterning the metal layer and the polysilicon layer in accordance with the circuit.

Claim 6

The method of claim 2 in which the insulating layer is essentially a deposited glass layer doped with phosphorus to a concentration of about 5 percent by weight.

Claim 7

The method of claim 2 in which the insulating layer is essentially a deposited glass layer doped with phosphorus to a concentration less than the saturation level.

Claim 8

The method of claim 3 in which the metal is essentially aluminum.

Claim 9

The method of claim 5 in which the gettering temperature is about 950 degrees C., and in which the sacrificial protective layer is essentially a deposited glass layer containing less than about 2 percent phosphorus by weight and having a sufficient thickness whereby any significant flow of the glass layer doped with phosphorus into the apertures during gettering is mechanically prevented by the presence of the polysilicon layer and the protective layer.

Claim 10

The method of claim 7 in which the protective layer is essentially TEOS deposited glass.

Claim 11

A process for making a plurality of MOS transistors at a top major surface of a silicon semiconductor body comparing the steps of: (a) forming relatively thick field oxide layer on areas of the top major surface located between GASAD regions of the transistors to be formed; (b) growing a relatively thin gate oxide layer in the GASAD regions; (c) forming and patterning an arsenic doped polysilicon layer, overlaid with a metal silicide layer, on top of the gate and field oxide layers in accordance with the pattern of the first level metallization of the desired integrated circuit, whereby the gate oxide layer is exposed at areas overlying the source and drain regions of the transistors to be formed in the semiconductor body; (d) introducing arsenic through the exposed areas of the gate oxide into the semiconductor body at the source and drain regions to form arsenic-doped source and drain regions; (e) forming and planarizing a P-glass layer having a phosphorus doping level below the saturation level, and forming apertures in the P-glass layer at locations thereof where electrical contacts to the source and drain regions and to the first level metallization are to be formed; (f) depositing another polysilicon layer for making these contacts; (g) implanting arsenic into the last-mentioned polysilicon layer; (h) forming a phosphorus-impervious glass layer on the top surface of the structure being built, and removing from the bottom surface any glass layers which have formed on the bottom surface; (i) gettering the structure by a heat treatment in an ambient atmosphere containing phosphorus; (j) removing the phosphorus-impervious glass layer everywhere from the top surface to expose the last-mentioned polysilicon layer; (k) depositing a metal layer upon the last-mentioned polysilicon layer; and (l) patterning the metal layer and the last-mentioned polysilicon layer to form source and drain metallization interconnections in accordance with the desired integrated circuit.

Claim 12

A process for making a plurality of MOS transistors at a top major surface of a silicon semiconductor body comparing the steps of: (a) forming relatively thick field oxide layer on areas of the top major surface located between GASAD regions of the transistors to be formed; (b) growing a relatively thin gate oxide layer in the GASAD regions; (c) forming and patterning an arsenic doped polysilicon layer, overlaid with a metal silicide layer, on top of the gate and field oxide layers in accordance with the pattern of the first level metallization of the desired integrated circuit, whereby the gate oxide layer is exposed at areas overlying the source and drain regions of the transistors to be formed in the semiconductor body; (d) introducing arsenic through the exposed areas of the gate oxide into the semiconductor body at the source and drain regions to form arsenic-doped source and drain regions; (e) forming and planarizing a P-glass layer having a phosphorus doping level below the saturation level, and forming apertures in the P-glass layer at locations thereof where electrical contacts to the source and drain regions and to the first level metallization are to be formed; (f) depositing another polysilicon layer for making these contacts; (g) implanting arsenic into the last-mentioned polysilicon layer; (h) forming a phosphorus-impervious glass layer on the top surface of the structure being built, and removing from the bottom surface any glass layers which have formed on the bottom surface; (i) gettering the structure by a heat treatment in an ambient atmosphere containing phosphorus; (j) removing the phosphorus-impervious glass layer everywhere from the top surface to expose the last-mentioned polysilicon layer; (k) depositing a metal layer upon the last-mentioned polysilicon layer; and (l) patterning the metal layer and the last-mentioned polysilicon layer to form source and drain metallization interconnections in accordance with the desired integrated circuit.

Claim 13

The method of claim 9 in which the P-glass layer contains about 5 percent phosphorus by weight.

Claim 14

The method of claim 9 in which the metal is aluminum.

Claim 15

The method of claim 10 in which the phosphorus-impervious glass layer is deposited from essentially phosphorus-free TEOS.