US4583190A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer based system for performing fast Fourier transforms
Assignee: DAROX Corp A DE CORP
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Filing: 1982-04-21
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Granted: 1986-04-15
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Expires: 2002-04-21
Abstract
Abstract A system for the on-line analysis and topographic display of human brain electrical activity which includes amplifying filtering and converter circuits for generating a plurality of signals, representing electrical activity at a plurality of predetermined data point locations on a patient's head in digital form, a first microprocessor and associated circuits to preprocess the digital signals into a predetermined format, and a second microprocessor and associated topographic map generator forming an image computation and display unit receiving the preprocessed digital signals as inputs from the image computation and display unit the topographic mag generator defining a map of a plan or elevation view of the brain containing a plurality of pixel points far in excess of the number of data points and interpolating the digital signals, so as to provide a value for each pixel on the map and providing the pixel information as outputs in synchronism with a horizontal and vertical scan, and a video monitor receiving the output of the image computation and display unit as an input.
Inventors
- 👤 Jesse Salb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:42
CPC Classifications
A; A61; A61B; A61B5/00; A61B5/24; A61B5/316; A61B5/369; A61B5/372; A61B5/374; A61B5/72; A61B5/7235; A61B5/7253; A61B5/7257; A61B5/7203; A61B5/7207
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
239 words
A fast Fourier transform (FFT) circuit comprising: (a) a microprocessor; (b) a program memory for said microprocessor; (c) a first random access memory for said microprocessor; (d) an address decoder for said first random access memory; (e) clock means for providing clock inputs to said microprocessor; (f) input/output ports, said units coupled together by means of address, data and control busses; (g) a plurality of signals in digital form to be transformed being an input to one of said input/output ports; (h) an FFT module receiving a digital word and performing a fast Fourier transform on said word; (i) a bidirectional buss transceiver for providing data to and receiving data from said FFT module having one of its data inputs coupled thereto; (j) an FFT random access memory coupled to said data and control busses, said data busses also coupled to the other data input of said bidirectional bus transceiver; (k) an FFT multiplexer coupling the address lines from said address bus for said random access memory into said FFT random access memory permitting inputting the addresses in normal order, and, upon selection, reverse order; and (l) means receiving an output from said address decoder and providing an input to said FFT multiplexer for said selecting between a normal order and a reverse order one for use during input of data to said FFT module and the other for use after data has been converted by said FFT module.
Claim 2
Dependent Claim
239 words
A fast Fourier transform (FFT) circuit comprising: (a) a microprocessor; (b) a program memory for said microprocessor; (c) a first random access memory for said microprocessor; (d) an address decoder for said first random access memory; (e) clock means for providing clock inputs to said microprocessor; (f) input/output ports, said units coupled together by means of address, data and control busses; (g) a plurality of signals in digital form to be transformed being an input to one of said input/output ports; (h) an FFT module receiving a digital word and performing a fast Fourier transform on said word; (i) a bidirectional buss transceiver for providing data to and receiving data from said FFT module having one of its data inputs coupled thereto; (j) an FFT random access memory coupled to said data and control busses, said data busses also coupled to the other data input of said bidirectional bus transceiver; (k) an FFT multiplexer coupling the address lines from said address bus for said random access memory into said FFT random access memory permitting inputting the addresses in normal order, and, upon selection, reverse order; and (l) means receiving an output from said address decoder and providing an input to said FFT multiplexer for said selecting between a normal order and a reverse order one for use during input of data to said FFT module and the other for use after data has been converted by said FFT module.
Claim 3
Dependent Claim
42 words
Apparatus according to claim 1 and further including means to convert the clock signal from said clock means into a signal of sufficient length to carry out the FFT in said module to thereby avoid slowing down processing by said first microprocessor.
Claim 4
Dependent Claim
62 words
Apparatus according to claim 2 wherein said means to convert comprise a monostable multivibrator receiving an enable input from one address line and a trigger input from a FFT select output of said first address decoder, said monostable multivibrator set to have a time out period equal to the period required to meet the input data hold requirements of the FFT module.
Claim 5
Independent Claim
223 words
A method of performing an Fast Fourier Transform (FFT) on an M point data segment comprising: (a) storing digital signals corresponding to the M points to be transformed in a random access memory; (b) transferring an N point data block from said first random access memory to an FFT module for performing a transform on N points, using a microprocessor and through a bidirection bus transceiver controlled by said microprocessor, where M is equal to N times P where P is an integer equal to or greater than 2; (c) performing an FFT in said FFT module on said N points under command of said microprocessor; (d) transferring the transformed N point data block from said FFT to an FFT random access memory through said bus transceiver using said microprocessor; (e) carrying out steps (b) to (d) P times so as to completely transform said M points of data; (f) unloading the transformed data from said FFT random access memory to said first random access memory using said microprocessor; and (g) multiplexing address lines into said FFT random access memory between a normal order and a reverse order, one of said orders being used during input of data to said FFT random access memory and the other during unloading of data from said FFT random access memory to said first random access memory.
Claim 6
Independent Claim
223 words
A method of performing an Fast Fourier Transform (FFT) on an M point data segment comprising: (a) storing digital signals corresponding to the M points to be transformed in a random access memory; (b) transferring an N point data block from said first random access memory to an FFT module for performing a transform on N points, using a microprocessor and through a bidirection bus transceiver controlled by said microprocessor, where M is equal to N times P where P is an integer equal to or greater than 2; (c) performing an FFT in said FFT module on said N points under command of said microprocessor; (d) transferring the transformed N point data block from said FFT to an FFT random access memory through said bus transceiver using said microprocessor; (e) carrying out steps (b) to (d) P times so as to completely transform said M points of data; (f) unloading the transformed data from said FFT random access memory to said first random access memory using said microprocessor; and (g) multiplexing address lines into said FFT random access memory between a normal order and a reverse order, one of said orders being used during input of data to said FFT random access memory and the other during unloading of data from said FFT random access memory to said first random access memory.
Claim 7
Dependent Claim
72 words
The method of claim 4 wherein said microprocessor has an internal clock signal, during one state of which data and addresses at the output of said microprocessor remain valid, and further including stretching said clock signal whom transferring signals to and from said FFT module to a signal of sufficient length to carry out data transfer with said FFT module to thereby avoid slowing down processing by said microprocessor at other times.
Claim 8
Dependent Claim
53 words
The method of claim 4, wherein said FFT module is capable of performing different sequences of sub-routines on the data supplied to it and further including selecting a sequence of sub-routines to be performed on said data by said FFT module through writing of an address to said FFT module with the microprocessor.
Claim 9
Dependent Claim
11 words
The method of claim 4 wherein N is equal to 32.
Claim 10
Dependent Claim
16 words
The method according to claim 4, wherein said FFT module transforms data using a decimation-in-frequency algorithm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |