US4559607A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arrangement to provide an accurate time-of-arrival indication for a plurality of received signals
Assignee: ITT Inc
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Filing: 1983-07-11
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Granted: 1985-12-17
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Expires: 2003-07-11
Abstract
Abstract The arrangement comprises N signal channels each responsive to a different one of N signals where N is an integer greater than one. Each of the N signal channels includes a sampling circuit to sample the associated one of the N signals by a different one of N phase clocks with each of the N phase clocks sampling a different one of the N signals at a predetermined different time uniformly spaced over a given time interval. A delay means is coupled to each of the sampling circuits to time align the outputs of each of the sampling circuits so that all sampled signal pulses are time shifted consistent with the associated sampling clock phases. A correlator is coupled to the output of each of the delay means to correlate the samples of the N signals with a reference signal. The output of the correlators are integrated to provide the indication of the time of arrival of the N signals.
Inventors
- 👤 Ning H. Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:42
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/709; G; G01; G01S; G01S11/00; G01S11/02; G01S11/08
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
104 words
An arrangement to provide an accurate time-of-arrival indication for N received signals, where N is an integer greater than one, comprising: N signal channels, each responsive to a different one of said N signals, each of said N channels including: first means to provide predetermined samples of the associated one of said N signals, and second means coupled to said first means to correlate said predetermined samples with a reference signal; and third means coupled to each of said second means to integrate the correlated output signals of each of said second means to provide said indication of said time-of-arrival of said N signals.
Claim 2
Dependent Claim
104 words
An arrangement to provide an accurate time-of-arrival indication for N received signals, where N is an integer greater than one, comprising: N signal channels, each responsive to a different one of said N signals, each of said N channels including: first means to provide predetermined samples of the associated one of said N signals, and second means coupled to said first means to correlate said predetermined samples with a reference signal; and third means coupled to each of said second means to integrate the correlated output signals of each of said second means to provide said indication of said time-of-arrival of said N signals.
Claim 3
Dependent Claim
32 words
An arrangement according to claim 1 wherein said third means includes a summing circuit coupled to each of said second means to provide said indication of said time-of-arrival of said N signals.
Claim 4
Dependent Claim
77 words
An arrangement according to claim 1, wherein each of said first means includes a sampling circuit to receive the associated one of said N signals and a given one of N-phase clocks, each of said N-phase clocks sampling a different one of said N signals at a predetermined different time uniformly spaced over a given time interval, and a delay means coupled to said sampling circuit to time align the outputs of each of said sampling circuits.
Claim 5
Dependent Claim
32 words
An arrangement according to claim 3, wherein said third means includes a summing circuit coupled to each of said second means to provide said indication of said time-of-arrival of said N signals.
Claim 6
Dependent Claim
34 words
An arrangement according to claim 3, wherein each of said second means includes a digital correlator coupled to an associated one of said delay means clocked by said given one of said N-phase clocks.
Claim 7
Dependent Claim
32 words
An arrangement according to claim 5, wherein said third means includes a summing circuit coupled to each of said digital correlators to provide said indication of said time-of-arrival of said N signals.
Claim 8
Dependent Claim
95 words
An arrangement according to claim 5, wherein each of said correlators includes a first shift register containing therein said reference signal, a second shift register coupled to said associated one of said delay means, output signals of said associated one of said delay means being clocked into said second shift register by said given one of said N-phase clocks, and comparison means coupled to each stage of each of said first and second shift registers to compare the contents of associated stages of said first and second shift registers and produce a resultant output signal.
Claim 9
Dependent Claim
40 words
An arrangement according to claim 7, wherein said third means includes a summing circuit coupled to each of said comparison means to sum each of said resultant output signals to provide said indication of said time-of-arrival of said N signals.
Claim 10
Dependent Claim
51 words
An arrangement according to claim 7, wherein said comparison means includes a plurality of EXCLUSIVE-OR gates equal in number to said associated stages of said first and second shift registers to enable comparison of the contents thereof, each of said gates producing at least a portion of said resultant output signal.
Claim 11
Dependent Claim
29 words
An arrangement according to claim 9, wherein said comparison means further includes a first summing circuit coupled to said plurality of EXCLUSIVE-OR gates to provide said resultant output signal.
Claim 12
Dependent Claim
34 words
An arrangement according to claim 10, wherein said third means includes a second summing circuit coupled to each of said first summing circuits to provide said indication of said time-of-arrival of said N signals.
Claim 13
Dependent Claim
43 words
An arrangement according to claim 9, wherein said comparison means further includes at least a first portion of said third means coupled to said plurality of EXCLUSIVE-OR gates to sum said portions of said resultant output signal to provide said resultant output signals.
Claim 14
Dependent Claim
32 words
An arrangement according to claim 12, wherein said third means includes a second portion coupled to each of said first portions to provide said indication of said time-of-arrival of said N signals.
Claim 15
Dependent Claim
28 words
An arrangement according to claim 13, wherein each of said first portions of said third means and said second portion of said third means is a summing circuit.
Claim 16
Dependent Claim
34 words
An arrangement according to claim 1, wherein each of said second means includes a digital correlator coupled to an associated one of said first means clocked by said given one of said N-phase clocks.
Claim 17
Dependent Claim
95 words
An arrangement according to claim 15, wherein each of said correlators includes a first shift register containing therein said reference signal, a second shift register coupled to said associated one of said first means, output signals of said associated one of said first means being clocked into said second shift register by said given one of said N-phase clocks, and comparison means coupled to each stage of each of said first and second shift registers to compare the contents of associated stages of said first and second shift registers and produce a resultant output signal.
Claim 18
Dependent Claim
51 words
An arrangement according to claim 16, wherein said comparison means includes a plurality of EXCLUSIVE-OR gates equal in number to said associated stages of said first and second shift registers to enable comparison of the contents thereof, each of said gates producing at least a portion of said resultant output signal.
Claim 19
Dependent Claim
29 words
An arrangement according to claim 17, wherein said comparison means further includes a first summing circuit coupled to said plurality of EXCLUSIVE-OR gates to provide said resultant output signal.
Claim 20
Dependent Claim
34 words
An arrangement according to claim 18, wherein said third means includes a second summing circuit coupled to each of said first summing circuits to provide said indication of said time-of-arrival of said N signals.
Claim 21
Dependent Claim
43 words
An arrangement accoding to claim 17, wherein said comparison means further includes at least a first portion of said third means coupled to said plurality of EXCLUSIVE-OR gates to sum said portions of said resultant output signal to provide said resultant output signals.
Claim 22
Dependent Claim
32 words
An arrangement according to claim 20, wherein said third means includes a second portion coupled to each of said first portions to provide said indication of said time-of-arrival of said N signals.
Claim 23
Dependent Claim
28 words
An arrangement according to claim 21, wherein each of said first portions of said third means and said second portion of said third means is a summing circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-16 | 1989-06-17 | 1989-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-16 | 1993-06-17 | 1993-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-16 | 1997-06-17 | 1997-12-17 | $7700.00 | Window Closed / Lapsed |