US4554564A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of manufacturing same, as well as a pick-up device and a display device having such a semiconductor device
Assignee: US Philips Corp
•
Filing: 1982-02-05
•
Granted: 1985-11-19
•
Expires: 2002-02-05
Abstract
Abstract The invention relates to a method for displaying a pattern on a resist using electron lithography. In particular, a cathode device having a matrix of semiconductor cathodes generates an electron beam which exposes a resist layer. The electron beam is generated by applying control signals to selected ones of the matrix of cathodes to cause electron emission therefrom.
Inventors
- 👤 Gerardus G. P. van Gorkom
- 👤 Arthur M. E. Hoeberechts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:28
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H01; H01J; H01J37/00; H01J37/30; H01J37/317; H01J37/3174; H01J37/3175; B82Y40/00; H01J1/00; H01J1/02; H01J1/30; H01J1/308; H01J2237/00; H01J2237/30; H01J2237/317; H01J2237/3175; H01J2237/31777; H01J2237/31781; H01J2237/31784
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
A method of displaying a pattern on a photoresist layer using electron lithography comprising the steps of generating an electron pattern from a matrix of cathodes formed in a semiconductor device comprising a silicon slice covered by a photoresist layer by applying control signals to selected ones of said cathodes to cause electron emission, and exposing said photoresist layer with said electron pattern, wherein each cathode of said matrix has two connection electrodes and an accelerating electrode, and wherein said cathodes providing electron emission are selected by applying a potential to their connection electrodes for generating electrons from each of said selected cathodes as an electron beam having an intensity dependent on a potential applied to said accelerating electrode of that cathode.
Claim 2
Independent Claim
122 words
A method of displaying a pattern on a photoresist layer using electron lithography comprising the steps of generating an electron pattern from a matrix of cathodes formed in a semiconductor device comprising a silicon slice covered by a photoresist layer by applying control signals to selected ones of said cathodes to cause electron emission, and exposing said photoresist layer with said electron pattern, wherein each cathode of said matrix has two connection electrodes and an accelerating electrode, and wherein said cathodes providing electron emission are selected by applying a potential to their connection electrodes for generating electrons from each of said selected cathodes as an electron beam having an intensity dependent on a potential applied to said accelerating electrode of that cathode.
Claim 3
Dependent Claim
33 words
A method according to claim 1, wherein said electron pattern generated by said matrix is reduced in scale by at least one electron lens, said electron pattern being imaged on said photoresist layer.
Claim 4
Independent Claim
24 words
A method according to one of claims 1 or 2, wherein said control signals applied to said selected cathodes are derived from shift registers.
Claim 5
Dependent Claim
46 words
A method according to claim 3, wherein said cathodes are arranged in an X-Y matrix having X and Y address lines, and wherein the content of said shift registers determine which X-lines and Y-lines will be driven to cause a desired pattern of cathodes to emit.
Claim 6
Independent Claim
27 words
A method according to one of claims 1 or 2, wherein said potential of said accelerating electrodes is adjusted by shift registers in combination with digital-to-analog converters.
Claim 7
Independent Claim
30 words
A method according to one of claims 1 or 2, wherein said control signals are derived from control electronics formed in the same semiconductor body as said matrix of cathodes.
Claim 8
Independent Claim
44 words
A method according to one of claims 1 or 2, wherein said connection electrodes are given a potential to create avalanche multiplication in an associated p-n junction, and said accelerating electrodes associated with said connection electtodes are simultaneously given a potential for accelerating electrons.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |