Phase demodulator including variable phase shifter for controlling reference carrier

Claim 2

A phase demodulator comprising: a first detector means for phase-detecting an input digital-signal-modulated carrier wave with a reference carrier wave supplied thereto; a variable phase shifter means for receiving said reference carrier wave and controlling its phase in response to a control signal; a second phase detector means for phase-detecting said input modulated carrier waves with the output of said variable phase shifter; means for recovering said reference carrier wave; multilevel discriminator means for multilevel discriminating outputs of said first and second detectors, said multilevel discriminator means comprising analog-to-digital (A/D) conversion means for receiving outputs of said first and second phase detector means and for providing corresponding first and second multi-bit digital signals, at least a portion of each multi-bit digital signal generated from each phase detector output representing demodulated data; and logic means for logically processing the output of the discriminator means and providing an orthogonality error signal as said control signal, said logic means comprising a first Exclusive OR (EOR) gate for receiving and combining selected bits from each of said multi-bit A/D converter output signals, a second EOR gate for receiving and combining different selected bits from each of said multi-bit A/D converter output signals, an adder means for adding the outputs of said first and second EOR gates to obtain said control signal.

Claim 3

A phase demodulator comprising: a first phase detector means for phase-detecting an input signal with a reference carrier wave supplied thereto, said input signal comprising a carrier wave modulated with a digital information signal; a variable phase shifter means for receiving said reference carrier wave and controlling its phase in response to a control signal; a second phase detector means for phase-detecting said input signals with the output of said variable phase shifter means; means for recovering said reference carrier wave; means for detecting non-orthogonality of the reference carrier wave supplied to said first phase detector means and the phase shifter output supplied to said secnd phase detector means, said means for detecting non-orthogonality comprising: first A/D conversion means for generating a first plurality of bits representing digital data contained in the output of said first phase detector means, and generating a further output bit; second A/D conversion means for generating a second plurality of output bits representing digital data contained in the output of said second phase detector means, and generating a further output bit; first logic means for logically combining said further output bit from said first A/D conversion means with at least one of said second plurality of output bits; second logic means for logically combining said further output bit from said second A/D conversion means with at least one of said first plurality of output bits; and means for combining outputs of said first and second logic means to obtain said control signal; and means responsive to said non-orthogonality detection for adjusting the value of said control signal.

Claim 4

A phase demodulator comprising: a first phase detector means for phase-detecting an input signal with a reference carrier wave supplied thereto, said input signal comprising a carrier wave modulated with a digital information signal; a variable phase shifter means for receiving said reference carrier wave and controlling its phase in response to a control signal; a second phase detector means for phase-detecting said input signals with the output of said variable phase shifter means; means for recovering said reference carrier wave; means for detecting non-orthogonality of the reference carrier wave supplied to said first phase detector means and the phase shifter output supplied to said secnd phase detector means, said means for detecting non-orthogonality comprising: first A/D conversion means for generating a first plurality of bits representing digital data contained in the output of said first phase detector means, and generating a further output bit; second A/D conversion means for generating a second plurality of output bits representing digital data contained in the output of said second phase detector means, and generating a further output bit; first logic means for logically combining said further output bit from said first A/D conversion means with at least one of said second plurality of output bits; second logic means for logically combining said further output bit from said second A/D conversion means with at least one of said first plurality of output bits; and means for combining outputs of said first and second logic means to obtain said control signal; and means responsive to said non-orthogonality detection for adjusting the value of said control signal.