US4544882A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for testing an integrated circuit chip without concern as to which of the chip's terminals are inputs or outputs
Assignee: Unisys Corp
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Filing: 1982-12-07
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Granted: 1985-10-01
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Expires: 2002-12-07
Abstract
Abstract Apparatus is disclosed which provides for testing a wide variety of different types of electrical circuit devices, such as PROM integrated circuit chips, with very little if any programming being required, and without concern as to which of the terminals of the chip are inputs or outputs. The testing apparatus achieves this result by taking advantage of the significant difference in the input and output impedances of most chips to permit treating the logical levels on both inputs and outputs of the chip in a like manner while generating a running signature output in response to a series of input test patterns, the resulting final signature obtained being indicative of the operation of the chip. Provision is also made for testing circuits having internal storage and/or requiring special power or clock inputs.
Inventors
- 👤 Laurence P. Flora
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
133 words
In apparatus for testing an electrical circuit having input and output terminals with significantly different input and output impedances, the combination comprising: test signal means for applying logical signals to the input and output terminals of said circuit; said test signal means having a driving impedance chosen in conjunction with said input and output impedances such that said driving impedance is low enough to cause an input terminal to receive an acceptable input logical signal having the same logical value as provided by said test signal means, while being high enough to cause an output terminal to provide an output logical signal having the same logical value as would normally be provided thereby in response to the input logical signals applied to the input terminals of the circuit by said test signal means.
Claim 2
Dependent Claim
133 words
In apparatus for testing an electrical circuit having input and output terminals with significantly different input and output impedances, the combination comprising: test signal means for applying logical signals to the input and output terminals of said circuit; said test signal means having a driving impedance chosen in conjunction with said input and output impedances such that said driving impedance is low enough to cause an input terminal to receive an acceptable input logical signal having the same logical value as provided by said test signal means, while being high enough to cause an output terminal to provide an output logical signal having the same logical value as would normally be provided thereby in response to the input logical signals applied to the input terminals of the circuit by said test signal means.
Claim 3
Dependent Claim
52 words
The invention in accordance with claim 1, wherein said test signal means is adapted to serially provide a plurality of different test signal patterns to the terminals of said circuit, and wherein said apparatus includes monitoring means for monitoring the signals appearing on said terminals in response to said test signal patterns.
Claim 4
Dependent Claim
52 words
The invention in accordance with claim 2, wherein said monitoring means includes function generating means for producing a running signature pattern which is a function of all of the outputs produced on said circuit terminals in response to the serial test patterns applied to the circuit terminals by said test signal means.
Claim 5
Dependent Claim
25 words
The invention in accordance with claim 3, wherein said apparatus includes means for synchronizing the operation of said test signal means and said monitoring means.
Claim 6
Dependent Claim
40 words
The invention in accordance with claim 3, wherein said function generating means combines the circuit terminal output pattern obtained in response to each test signal pattern with the most recent running signature pattern to produce an updated running signature pattern.
Claim 7
Dependent Claim
46 words
The invention in accordance with claim 5, wherein said function generating means includes a programmable read only memory to which each circuit terminal output pattern is applied along with the most recent running signature pattern produced by said memory for producing an updated running signature pattern.
Claim 8
Dependent Claim
38 words
The invention in accordance with claim 6, wherein said apparatus includes display means for displaying the final running signature produced by said monitoring means after the last test signal pattern has been produced by said test signal means.
Claim 9
Dependent Claim
32 words
The invention in accordance with claim 1, 2, 3, 4, 5, 6 or 7, wherein said signal test means provides for applying all possible test patterns to the terminals of said circuit.
Claim 10
Dependent Claim
35 words
The invention in accordance with claim 1, 2, 3, 4, 5, 6 or 7, wherein said signal test means includes an N-bit binary counter wherein N is equal to the number of terminals being tested.
Claim 11
Dependent Claim
29 words
The invention in accordance with claim 1, 2, 3, 4, 5, 6 or 7, wherein said apparatus includes means for applying a clock to a terminal of said circuit.
Claim 12
Dependent Claim
31 words
The invention in accordance with claim 1, 2, 3, 4, 5, 6 or 7, wherein said apparatus includes means for applying a source of power to a terminal of said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-30 | 1989-04-01 | 1989-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-30 | 1993-04-01 | 1993-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-30 | 1997-04-01 | 1997-10-01 | $7700.00 | Window Closed / Lapsed |