US4528634A
Expired / Lapsed
US
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Bit pattern generator
Assignee: Hitachi Ltd
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Filing: 1982-10-08
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Granted: 1985-07-09
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Expires: 2002-10-08
Abstract
Abstract A bit pattern generator includes two memories which are provided for storing a bit pattern for a scanning line produced from design data. When a bit pattern is created and stored in one of the memories, the previously created and stored bit pattern is read out from the other memory. For the creation of each bit pattern, a scanning line is divided into a plurality of bytes. Model patterns of bit patterns existing in the respective bytes are stored in a ROM. From the combination of start point and end point addresses specifying the byte positions and the ROM addresses, a ROM address for each byte is logically determined so that any model patterns in the ROM are sequentially stored in the first mentioned memories.
Inventors
- 👤 Kozo Nakahata
- 👤 Ikuo Kawaguchi
- 👤 Kazuo Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:58
CPC Classifications
H; H10; H10P; H10P95/00; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G09; G09G; G09G5/00; G09G5/42
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
382 words
A bit pattern generator for generating, bit patterns of n bytes each including m bits, on the basis of a plurality of sets of pattern information each of which includes a start point address X s having a start point byte address X sH and a start point bit address X sL and an end point address X e having an end point byte address X eH and an end point bit address X eL , comprising: a ROM having preliminarily stored model patterns in byte units any one of which is read out therefrom by designating a pair of address signals A L and A H ; a first latch circuit for holding said start point address X s and providing said start point byte address X sH and said start point bit address X sL at its first and second outputs, respectively; a second latch circuit holding said end point address X e and providing said end point byte address X eH and said end point bit address X eL at its first and second outputs, respectively; an address counter for receiving said start point byte address X sH from said first latch circuit to provide a byte address X CNT ; logical operation means which receives said start point byte address X sH and said start point bit address X sL from said first latch circuit, said end point byte address X eH and said end point bit address X eL from said second latch circuit, and said byte address X CNT from said address counter to produce an output representative of a comparison between X eH and X CNT and logical operation outputs representative of said pair of address signals A L and A H , said address signals A L and A H being supplied to said ROM; a sequence control circuit for receiving the comparison output from said logical operation means to increment said address counter when X eH ≠X CNT ; RAM means having a storage area of at least m bits by n bytes, the writing position to said RAM means being controlled by the byte address from said address counter; and a gate circuit located between said ROM and said RAM means for writing the output of said ROM into said RAM means.
Claim 2
Dependent Claim
382 words
A bit pattern generator for generating, bit patterns of n bytes each including m bits, on the basis of a plurality of sets of pattern information each of which includes a start point address X s having a start point byte address X sH and a start point bit address X sL and an end point address X e having an end point byte address X eH and an end point bit address X eL , comprising: a ROM having preliminarily stored model patterns in byte units any one of which is read out therefrom by designating a pair of address signals A L and A H ; a first latch circuit for holding said start point address X s and providing said start point byte address X sH and said start point bit address X sL at its first and second outputs, respectively; a second latch circuit holding said end point address X e and providing said end point byte address X eH and said end point bit address X eL at its first and second outputs, respectively; an address counter for receiving said start point byte address X sH from said first latch circuit to provide a byte address X CNT ; logical operation means which receives said start point byte address X sH and said start point bit address X sL from said first latch circuit, said end point byte address X eH and said end point bit address X eL from said second latch circuit, and said byte address X CNT from said address counter to produce an output representative of a comparison between X eH and X CNT and logical operation outputs representative of said pair of address signals A L and A H , said address signals A L and A H being supplied to said ROM; a sequence control circuit for receiving the comparison output from said logical operation means to increment said address counter when X eH ≠X CNT ; RAM means having a storage area of at least m bits by n bytes, the writing position to said RAM means being controlled by the byte address from said address counter; and a gate circuit located between said ROM and said RAM means for writing the output of said ROM into said RAM means.
Claim 3
Dependent Claim
46 words
A bit pattern generator according to claim 1, wherein said sequence control circuit operates to provide "0" data to said gate circuit prior to an writing operation to said RAM means so that "0"s are initially stored in the entire storage area of said RAM means.
Claim 4
Dependent Claim
32 words
A bit pattern generator according to claim 1, wherein said RAM means includes a pair of RAMs the writing and reading operations of which are alternately controlled by said sequence control circuit.
Claim 5
Dependent Claim
50 words
A bit pattern generator according to claim 3, wherein the RAM in a writing mode is connected at its output to a bit latch circuit, and the output of said bit latch circuit being supplied to said gate circuit to produce a logical sum with the output of said ROM.
Claim 6
Dependent Claim
223 words
A bit pattern generator according to claim 1, wherein said logical operation means includes a first comparator for comparing said byte address X CNT from said address counter and said start point byte address X sH from said first latch circuit to provide an output indicative of X sH =X CNT and an output representative of X sH <X CNT , a second comparator for comparing said byte address X CNT from said address counter and said end point byte address X eH from said second latch circuit to provide an output indicative of X eH >X CNT and an output indicative of X eH =X CNT , a set of AND gates for providing the start point bit address X sL from said first latch circuit as the address signal A L when said first comparator provides the X sH =X CNT output and for providing "0"s as the address signal A L when said first comparator provides the X sH <X CNT output, and a set of OR gates for providing "F"s as the address signal A H when said second comparator provides the X eH >X CNT output and for providing the end point bit address X eL from said second latch circuit as the address signal A H when said second comparator provides the X eH =X CNT output.
Claim 7
Dependent Claim
56 words
A bit pattern generator according to claim 5, wherein said sequence control circuit is applied with the X sH <X CNT output from said first comparator and the X eH >X CNT output from said second comparator to provide "FFFF" data to said gates when a relation of X SH <X CNT <X eH is satisfied.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-08 | 1989-01-07 | 1989-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-08 | 1993-01-07 | 1993-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-08 | 1997-01-07 | 1997-07-09 | $7700.00 | Window Closed / Lapsed |