High speed bus architecture

Claim 2

A bus architecture system for selectively connecting a plurality of user devices to each other, comprising, priority interrupt encoder means (121) for receiving and prioritizing interrupt signals from one or more of said user devices when one or more of said user devices attempt to access another user device, control bus means interconnecting each of said user devices, and test means (123) connected to said control bus means and said encoder means for determining when said encoder means can gain access to said control bus means as a function of the status of said control bus means so that one user device can gain access to another user device.

Claim 3

The system recited in claim 1 including, data bus means interconnecting each of said user devices, and control means connected to said control bus means to selectively enable said data bus means to activate a pair of said user devices for data transfer therebetween as determined by said encoder means.

Claim 4

The system recited in claim 1 wherein, said test means is connected to said control bus status to test whether said control bus is busy and to selectively permit access thereto only when not busy.

Claim 5

The system recited in claim 1 wherein, said encoder means comprises means for receiving interrupt requests from said user devices, and register means for storing interrupt requests as received and prioritized by said encoder means.

Claim 6

The system recited in claim 2 wherein, said control means includes register means connected to each of said user devices to selectively supply address signals to said pair of said user devices.

Claim 7

The system recited in claim 2 including, multiplexer means connected to supply signals to the input of said control means and to receive output signals from said control means and from said control bus.

Claim 8

The system recited in claim 1 wherein, each of said user devices includes register means for storing therein a master address for itself and a slave address for another user device which may communicate therewith.

Claim 9

The system recited in claim 1 including, input means for selectively storing information within said user devices via said control bus.

Claim 10

The system recited in claim 4 wherein, said register means is a FIFO type register which is connected to supply signals to said control bus.

Claim 11

The system recited in claim 2 wherein, said control means suplies signals to said user devices via said data bus means, and said user devices selectively supply signals to said control means via said data bus means whereby said control means and said user devices determine which of said user devices are to be activated.

Claim 12

A bus architecture system comprising, a plurality of user devices, a control bus connected to each of said user devices to permit addressing communication between said user devices, a data bus connected to each of said user devices for selectively transferring information between said user devices, interrupt encoder means connected to receive interrupt signals from said control bus wherein said interrupt signals signify that one user device is attempting to access another user device via said control bus, storage means for storing said interrupt signals until said control bus is not busy, and test means connected to said control bus and to said encoder means to selectively operably connect said encoder means to said control bus only when said control bus is not busy.

Claim 13

A bus architecture system comprising, a plurality of user devices, a control bus connected to each of said user devices to permit addressing communication between said user devices, a data bus connected to each of said user devices for selectively transferring information between said user devices, interrupt encoder means connected to receive interrupt signals from said control bus wherein said interrupt signals signify that one user device is attempting to access another user device via said control bus, storage means for storing said interrupt signals until said control bus is not busy, and test means connected to said control bus and to said encoder means to selectively operably connect said encoder means to said control bus only when said control bus is not busy.

Claim 14

The system recited in claim 11 including, supervisory means connected to said data bus to control the operation thereof and to said control bus to receive control signals therefrom.

Claim 15

The system recited in claim 11 wherein, each of said user devices has a separate identification designation (ID).

Claim 16

The system recited in claim 13 wherein, each of said user devices includes internal storage means for storing the ID of at least one other user device.

Claim 17

A bus architecture system for permitting intercommunication between a plurality of separate user devices, comprising, control bus means connected to each of said user devices to permit any user device to access any other user device by means of interrupt (address) signals, encoder means connected to said control bus means to receive said interrupt (address) signals and store same in the order received, test means connected to said encoder means and to said control bus means such that said encoder means can be enabled to place a stored interrupt (address) signal on said control bus only when said control bus is not busy, as determined by said test means, and data transfer means connected to each of said user devices to transfer data information signals between at least two user devices in response to an interrupt (address) signal which is received from said control bus.

Claim 18

A bus architecture system for permitting intercommunication between a plurality of separate user devices, comprising, control bus means connected to each of said user devices to permit any user device to access any other user device by means of interrupt (address) signals, encoder means connected to said control bus means to receive said interrupt (address) signals and store same in the order received, test means connected to said encoder means and to said control bus means such that said encoder means can be enabled to place a stored interrupt (address) signal on said control bus only when said control bus is not busy, as determined by said test means, and data transfer means connected to each of said user devices to transfer data information signals between at least two user devices in response to an interrupt (address) signal which is received from said control bus.

Claim 19

The system recited in claim 15 wherein, said encoder means is operable to prioritize the interrupt (address) signals supplied thereto in the event of the concurrent application of two or more such interrupt (address) signals.

Claim 20

The system recited in claim 15 wherein said test means includes logic circuit means to supply a signal to said encoder means to permit the interrupt (address) signals stored therein to be placed on said control bus.

Claim 21

The system recited in claim 17 wherein, said encoder means includes a FIFO register for storing said interrupt (address) signals in the prioritized order.