Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit

Claim 1

An I/O controller adapted to be coupled to the I/O channel bus of a host processor and to an I/O unit for transferring data between the host processor and the I/O unit and comprising: a microprocessor for supervising data transfer activities and including circuitry for providing for each of its machine cycles an address set-up indicative pulse denoting the occurrence of the microprocessor address set-up interval; a microprocessor I/O bus coupled to the microprocessor and adapted to be coupled to the I/O unit; a random access storage mechanism for storing data; cycle steal control circuitry responsive to the occurrence of both predetermined address bits on the host processor channel bus and an address set-up indicative pulse from the microprocessor for producing during the microprocessor address set-up interval an allow host connect signal; address selector circuitry for selectively transferring address bits from either the microprocessor bus or the host processor channel bus to the address circuitry of the random access storage mechanism and responsive to the occurrence of the allow host connect signal for selecting the host processor address bits for such transfer; first data transfer circuitry responsive to the occurrence of the allow host connect signal for providing a data transfer path between the host processor channel bus and the random access storage mechanism; and second data transfer circuitry operative during the absence of the allow host connect signal for providing a data transfer path between the random access storage mechanism and the microprocessor bus.