Method of making a monolithic integrated circuit comprising at least one pair of complementary field-effect transistors and at least one bipolar transistor

Claim 1

A method for the monolithic integration of a semiconductor circuit having at least one pair of complementary field effect transistors (FET's) having gate electrodes of an n-type material and at least one NPN bipolar transistor comprising the steps of: forming a first substrate region for said bipolar transistor and a second substrate region for a P-channel FET in one surface of a p-type semiconductor substrate; providing a thick oxide layer on said surface having an opening formed in the areas of said first substrate regions a second opening formed in the area of said second substrate region and a third opening formed in the area of an N-channel FET; closing said opening and said first and second openings with thin oxide layers during a gate oxidation process; exposing said surface in said opening to form an emitter region area and a collector contact region area of said bipolar transistor with a stripelike configuration of said thin oxide layer disposed between said emitter region area and said collector contact region and dividing said opening; implanting impurities of the conductivity type of said substrate into said emitter region area and an adjacent portion of said bipolar transistor below said thin oxide layer; depositing an n-type electrode material layer; etching away unwanted portions of said n-type electrode material layer to form gate electrodes for said pair of FET's, and emitter and collector electrodes for said bipolar transistor; implanting impurities of the regions of the N-channel FET by masked ion implantation; implanting impurities of the regions of the P-channel FET by masked ion implantation while simultaneously implanting impurities of a base contact region between said emitter and collector electrodes; and subjecting said substrate to a high temperature to activate said implanted impurities of said P and N channel FET's and to diffuse impurities in said emitter region area from said emitter electrode and to diffuse impurities in said collector contact region area from said collector electrode.

Claim 2

A method for the monolithic integration of a semiconductor circuit having at least one pair of complementary field effect transistors (FET's) having gate electrodes of an n-type material and at least one NPN bipolar transistor comprising the steps of: forming a first substrate region for said bipolar transistor and a second substrate region for a P-channel FET in one surface of a p-type semiconductor substrate; providing a thick oxide layer on said surface having an opening formed in the areas of said first substrate regions a second opening formed in the area of said second substrate region and a third opening formed in the area of an N-channel FET; closing said opening and said first and second openings with thin oxide layers during a gate oxidation process; exposing said surface in said opening to form an emitter region area and a collector contact region area of said bipolar transistor with a stripelike configuration of said thin oxide layer disposed between said emitter region area and said collector contact region and dividing said opening; implanting impurities of the conductivity type of said substrate into said emitter region area and an adjacent portion of said bipolar transistor below said thin oxide layer; depositing an n-type electrode material layer; etching away unwanted portions of said n-type electrode material layer to form gate electrodes for said pair of FET's, and emitter and collector electrodes for said bipolar transistor; implanting impurities of the regions of the N-channel FET by masked ion implantation; implanting impurities of the regions of the P-channel FET by masked ion implantation while simultaneously implanting impurities of a base contact region between said emitter and collector electrodes; and subjecting said substrate to a high temperature to activate said implanted impurities of said P and N channel FET's and to diffuse impurities in said emitter region area from said emitter electrode and to diffuse impurities in said collector contact region area from said collector electrode.