Real-time data sampling with memory sharing by high speed I/O processor and cycle stealing support processor

Claim 1

A digital data processor, for real-time processing of data samples, comprising: at least one data input adapted to receive input digital data samples; at least one data output adapted to output processed digital data samples; a first processor coupled between said data input and data output for performing processing operations on the data and adapted to operate with a plurality of machine cycles for each input data sample; a second processor for performing support operations in respect of the data; control input means connected to the second processor for input of control information; a common memory section accessible to and by both said first processor and said second processor; data bus means connecting said processors and said memory for transferring data therebetween; address bus means connected to said processors and said memory for addressing appropriate memory locations; and said first processor including program control means for controlling the operation of said processor and for providing addresses on said address bus means; means connecting said processors whereby said first processor signals to said second processor the coming of one predetermined machine cycle between input samples, during which cycle said first processor relinguishes control of said address and data bus means and carries out operations not requiring access to said common memory section; wherein said second processor is adapted to control said address bus means and said data bus means for said predetermined machine cycle whereby data can be transferred between said common memory section and said first processor without interrupting the processing performed by said first processor.